Embedded Ferroelectric Memory Cell Layout for Dense FinFET ICs
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in integrating memory devices within complex integrated circuits while maintaining efficient production and reducing costs, as existing methods struggle to scale down to smaller geometries without compromising performance.
Innovation Solution
A semiconductor structure is developed with a memory device embedded in an interconnection structure, utilizing a FinFET configuration with a ferroelectric capacitor for data storage, enabling precise patterning through photolithography and self-aligned processes to achieve smaller feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices are integrated within complex integrated circuits using existing methods, then functional density increases, but manufacturing precision deteriorates when scaling down to smaller geometries
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the final memory device pattern, using it as a template for subsequent self-aligned deposition processes. This preliminary mandrel is removed after serving its patterning function, enabling precise feature formation without requiring high-precision alignment at each subsequent step.
Solution Approach 2:
The patent introduces an intermediary mandrel structure that mediates between the substrate and the final memory device pattern. This intermediary element enables indirect pattern transfer through self-aligned material deposition, avoiding the need for direct high-precision photolithographic alignment at each stage.
2Productivity
If geometry size is decreased to increase functional density, then productivity improves, but device complexity increases
Solution Approach 1:
The patent segments the memory device structure into distinct functional components (mandrel, spacer, ferroelectric capacitor, transistor) that can be formed through separate self-aligned processes. This segmentation allows each component to be optimized independently while maintaining overall compactness, enabling smaller geometries without proportionally increasing complexity.
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional self-aligned structures, using vertical spacer formation and stacked capacitor configurations. This dimensional change enables increased functional density within smaller footprints by utilizing the third dimension rather than solely reducing lateral dimensions.
3Manufacturing precision
If self-aligned processes are used to achieve smaller feature sizes, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where previously deposited structures automatically serve as alignment references for subsequent deposition steps. The mandrel and spacer structures self-align subsequent materials without requiring external alignment systems, achieving high precision while the process complexity is managed through the self-organizing nature of the deposition sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of memory devices in advanced ICs, enhancing functional density and reducing costs by leveraging smaller geometries and improved manufacturing efficiency.
Implementation Method 1
utilizing a FinFET configuration with a ferroelectric capacitor for data storage, enabling precise patterning through photolithography
Data Source
AI summary
A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.