Embedded FIFO Logic Circuit for High-Speed Clock Cycle Utilization
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Solution Overview
Problem
Traditional flip-flop chain architectures in memory devices are inefficient in performing combination logic operations due to time wastage in each flip-flop stage and inability to utilize available clock cycles effectively, especially when the number of flip-flop stages is not aligned with the number of combination logic stages.
Innovation Solution
A FIFO stack circuit with a combination logic circuit that uses an input ring counter and output ring counter circuit to manage data flow and perform combination logic operations, allowing for high-speed calculations without the inefficiencies of previous architectures by optimizing the use of clock periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chained flip-flop architecture is used to perform combination logic operations, then the logic operations can be performed in stages, but time is wasted in each flip-flop stage due to setup time and clock signal delays
Solution Approach 1:
The patent extracts the combination logic circuit from the traditional chained flip-flop architecture and embeds it directly within the FIFO stack circuit. This removes the logic operations from the time-constrained flip-flop stages, allowing the FIFO to operate at full speed while the embedded logic processes data in parallel without adding delay to the critical path.
Solution Approach 2:
The patent merges the combination logic circuit with the FIFO stack circuit into a single integrated structure. The logic circuit is embedded within the FIFO, allowing data to be processed through the logic operations while residing in the FIFO buffer, eliminating the need for separate flip-flop stages and reducing overall operation time.
2Adaptability or versatility
If the number of flip-flop stages is not aligned with the number of combination logic stages, then the architecture becomes flexible, but available clock cycles cannot be utilized effectively
Solution Approach 1:
The patent implements a dynamic architecture where the FIFO stack depth and logic circuit configuration can be independently optimized. The FIFO can be sized to match any latency requirement, and the combination logic can process data at its own optimal speed, allowing the system to adapt to different clock cycle requirements without being constrained by fixed stage alignments.
Solution Approach 2:
The patent adds a temporal dimension to the data processing by using the FIFO buffer to store intermediate results across multiple clock cycles. This allows the combination logic to operate asynchronously with respect to the clock, processing data at its own pace while the FIFO absorbs timing mismatches, thereby achieving both flexibility and full clock cycle utilization.
3Duration of action of moving object
If multiple combination logic stages are performed during a single clock cycle, then latency is reduced, but timing constraints become more stringent and difficult to meet
Solution Approach 1:
The patent segments the combination logic operations into smaller sub-operations that can be performed in parallel within the embedded logic circuit. By breaking down complex multi-stage logic into concurrent simpler operations, the overall latency is reduced without requiring multiple clock cycles, and the timing constraints remain manageable through careful logic design.
Data Source
AI summary
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.