Embedded Filters in Multilayer Electronic Structures
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Solution Overview
Problem
The existing 'drill & fill' technology for creating vias in IC substrates and interposers is limited by low throughput, high costs, difficulty in achieving high-density arrays of varying sizes and shapes, rough laser-drilled via walls, and challenges in uniform copper filling, which affects electrical reliability and miniaturization efforts in electronic components.
Innovation Solution
The use of pattern plating and panel plating methodologies to fabricate copper via posts in a dielectric matrix, allowing for the creation of shaped vias and enabling the integration of capacitors and inductors within the substrate, which can be used to form filters, by depositing metal into photo-resist patterns and laminating with a polymer matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is used to create vias, then via channels can be formed, but the side walls become rough and tapered, reducing effective diameter and electrical contact quality
Solution Approach 1:
The patent replaces the mechanical laser drilling process with an electrochemical etching process. Instead of using laser energy to ablate material and create rough, tapered holes, the invention uses controlled electrochemical reactions to dissolve metal and form vias with smooth, uniform cylindrical walls. This substitution eliminates the fundamental limitation of laser drilling while maintaining via formation capability.
Solution Approach 2:
The patent changes the physical and chemical parameters of the via formation process by transitioning from thermal/laser-based drilling to electrochemical etching. By controlling electrochemical parameters such as current density, electrolyte composition, and etching time, the process achieves precise control over via dimensions and surface quality, producing smooth walls and consistent cylindrical shapes that improve electrical contact reliability.
2Reliability
If drill & fill technology is used, then vias can be created, but throughput rate is limited and fabrication costs become prohibitive
Solution Approach 1:
The patent performs preliminary patterning of the photoresist layer to define all via locations and dimensions before the electrochemical etching process. This pre-planning allows multiple vias to be formed simultaneously in parallel across the entire substrate, rather than drilling each via individually. The preliminary photoresist pattern serves as a mask that enables batch processing, dramatically increasing throughput while maintaining via quality consistency.
3Manufacturing precision
If laser drilling is used, then via channels are created, but uniform copper filling is difficult especially for large via channels near smaller vias
Solution Approach 1:
The patent replaces the mechanical laser drilling process with electrochemical etching, which produces via channels with uniform cylindrical geometry and smooth surfaces. This geometric uniformity eliminates the tapering effect inherent in laser drilling, creating via channels that have consistent cross-sectional area throughout their length. Such uniform geometry enables uniform copper deposition during the filling process, as the electrochemical filling can proceed evenly without the geometric complications of tapered or irregular via shapes.
4Adaptability or versatility
If different sized via channels are drilled and filled, then various via sizes can be achieved, but dimpling or overfill problems are exasperated as deposition cannot be optimized for different sizes simultaneously
Solution Approach 1:
The patent uses parameter changes in the photoresist patterning process to define different via sizes before electrochemical etching. By varying the photoresist pattern dimensions, the etching process creates via channels of different diameters and shapes. The electrochemical filling process then responds to these geometric parameters, allowing uniform copper deposition in each via type. The filling parameters can be optimized for each via size category, achieving uniform fills across different via dimensions without the dimpling or overfill problems associated with laser drilling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the cost-effective fabrication of high-density, high-reliability electronic structures with varied via shapes and sizes, facilitating the integration of passive components like filters, thereby supporting the miniaturization and performance requirements of advanced electronic devices.
Implementation Method 1
laser to drill holes through the subsequently laid down dielectric substrate
Implementation Method 2
The filling process of the drilled via holes is usually achieved by copper electroplating
Data Source
AI summary
A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one inductor is formed in at least one of the at least one feature layer and the adjacent via layer by electroplating copper into a pattern of photoresist stripping away the photoresist and laminating.