Embedded Flash Control Gate Structure for Higher Writing Efficiency
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Solution Overview
Problem
Conventional methods for forming a control gate in embedded flash using a high-k metal gate process are difficult, leading to poor writing efficiency in the resulting embedded flash.
Innovation Solution
A semiconductor structure is designed with a control gate structure comprising a high-k dielectric layer and a metal gate, where the width of the top portion is greater than the bottom portion, formed through a series of recesses and replacements, enhancing writing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a relatively large doped region is disposed in a substrate to replace the function of the control gate, then the control gate can be formed without using a high-k metal gate process, but the writing efficiency of the embedded flash becomes poor
Solution Approach 1:
The patent changes the material parameters of the control gate from conventional materials to high-k metal gate materials (such as hafnium oxide, tantalum oxide). This parameter change enables the control gate to achieve the required electrical characteristics with a smaller physical size, thus improving writing efficiency while maintaining ease of manufacture through the high-k material properties
Solution Approach 2:
The patent employs composite material structure by combining high-k dielectric layer with metal gate layer. This composite structure provides both the high dielectric constant needed for effective control gate function and the electrical conductivity required for efficient writing operations, resolving the contradiction between manufacturing ease and writing efficiency
2Productivity
If a control gate is formed using a high-k metal gate process, then the writing efficiency of the embedded flash can be improved, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent applies preliminary action by forming the high-k dielectric layer and metal gate layer as part of the existing CMOS fabrication process flow, integrating the HKMG formation into standard manufacturing steps. This preliminary integration reduces the complexity of the overall manufacturing process while achieving improved writing efficiency
Solution Approach 2:
The high-k metal gate structure serves multiple functions: it acts as the control gate for the embedded flash memory cell, provides gate control for adjacent CMOS transistors, and enables both high-efficiency writing operations and standard manufacturing processes. This multi-functionality resolves the contradiction by making the HKMG structure universally applicable
Data Source
AI summary
A semiconductor structure includes a substrate and a memory element. The memory element is disposed on the substrate and includes a floating gate, a tunnel dielectric layer, a control gate structure, an inter-gate oxide layer, an erase gate, and a word line. The floating gate is disposed on the substrate. The tunnel dielectric layer is disposed between the floating gate and the substrate. The control gate structure is disposed on the floating gate. The control gate structure includes a high-k dielectric layer and a metal gate, and a width of a top portion of the control gate structure is greater than a width of a bottom portion of the control gate structure. The inter-gate oxide layer is disposed between the floating gate and the control gate structure. The erase gate is disposed on one side of the floating gate. The word line is disposed on the other side of the floating gate. A manufacturing method of a semiconductor structure is also provided.