Device-Region Layout for Embedded Flash Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of silicide on the sidewalls of memory device regions during the silicide process leads to leakage paths, causing read and write failures, and the recessing of the isolation structure reduces the etch process window, resulting in inaccurate formation of word lines and potential electrical shorting.
Innovation Solution
An enhanced device-region layout where the word lines overlie the device-region sidewalls, preventing silicide formation and ensuring a uniform etch process by maintaining a planar surface, thus reducing leakage current and enlarging the etch process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the isolation structure is recessed to accommodate device regions, then device integration is improved, but the etch process window is reduced leading to inaccurate word line formation
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer over the recessed isolation structure before depositing the word line material. This pre-flattening step ensures that subsequent etching processes occur on a uniform surface, maintaining etch process window and word line formation accuracy while preserving the benefits of recessed isolation for device integration.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary between the recessed isolation structure and the word line formation process. This intermediate layer compensates for the surface non-uniformity created by recessing, allowing both device integration and manufacturing precision to be achieved simultaneously.
2Reliability
If silicide process is performed on device region sidewalls, then contact resistance is reduced, but leakage paths are formed causing read and write failures
Solution Approach 1:
The patent extracts or removes the device region sidewalls from the silicide formation process by designing the isolation structure to extend laterally and underlie the word lines. This geometric configuration prevents silicide deposition on sidewalls that would create leakage paths, while still allowing silicide to form on intended contact regions for maintaining low contact resistance.
Solution Approach 2:
The patent converts the potentially harmful effect of silicide formation on sidewalls into a beneficial outcome by using the isolation structure's lateral extension to block silicide deposition. The same geometric feature that prevents harmful sidewall silicide also ensures proper word line alignment and prevents leakage, turning a process challenge into a design advantage.
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.