Embedded Flash Memory Redundancy in DRAM Peripheral Area
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Solution Overview
Problem
Existing DRAM chips require significant area for redundant efuse or laser fuse, which are not rewritable and require additional high-voltage circuit design, necessitating a more compact and reliable embedded device for redundancy and testing compatible with DRAM manufacturing processes.
Innovation Solution
A DRAM device with embedded flash memory is fabricated using a semiconductor substrate with a DRAM array region and a peripheral region, featuring an ONO storage structure, flash memory gate, and transistors, where the ONO layer is patterned and contact holes are etched to form conductive layers and bit lines, enabling a compact and rewritable redundancy solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant efuse or laser fuse is provided in DRAM chip, then chip repair functionality is provided, but chip area is significantly occupied and high-voltage circuit design is required
Solution Approach 1:
The patent merges the redundancy function with the existing DRAM manufacturing process by embedding a fuse structure within the bit line formation process. The fuse is created using the same conductive layer deposition and patterning steps as the bit line, eliminating the need for separate redundancy circuitry and reducing chip area occupation.
Solution Approach 2:
The conductive layer serves multiple functions: it forms both the bit line for normal DRAM operation and the fuse structure for redundancy purposes. This multi-functionality eliminates the need for dedicated redundancy circuits, reducing overall chip area while maintaining repair capabilities.
2Area of stationary object
If laser fuse is used instead of efuse, then chip area is reduced, but additional high-voltage circuit design is required
Solution Approach 1:
The fuse structure is designed to be blown using the existing DRAM write operation voltages without requiring additional high-voltage circuitry. The fuse utilizes the same voltage levels already present in the DRAM operation, making the redundancy function self-service and eliminating complex high-voltage design requirements.
3Reliability
If traditional redundant fuse is used, then chip repair is enabled, but the fuse is not rewritable
Solution Approach 1:
The fuse structure is designed with dynamic characteristics that allow it to be reconfigured. By using a conductive layer that can be selectively removed or modified through standard DRAM operations, the fuse can be rewritten or reconfigured, providing adaptability while maintaining repair functionality.
Data Source
AI summary
A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.