Embedded Flash Memory Gate Fabrication Sequence
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Solution Overview
Problem
Conventional methods for forming embedded flash memory devices often result in damaged control gate surfaces due to insufficient thickness of the BARC and photoresist layers, leading to performance issues in the storage units.
Innovation Solution
The method involves forming a gate on the logic region first, followed by the control gate in the storage region, with a conformal gate material layer and a patterned mask layer to ensure sufficient thickness and protection during etching, avoiding the formation of grooves and subsequent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the control gate is formed first in the storage region, then the control gate structure can be established early, but the BARC and photoresist layers become too thin and cause damage to the control gate surface during subsequent etching
Solution Approach 1:
The gate structure is formed in the logic region first before forming the control gate in the storage region. This preliminary formation of the gate structure provides a foundation that allows subsequent layers (BARC and photoresist) to be applied with sufficient thickness, preventing damage to the control gate surface during etching while maintaining process efficiency
Solution Approach 2:
The formation process is divided into distinct stages: first forming the gate structure in the logic region, then forming the control gate in the storage region. This segmentation allows each region to be processed independently with appropriate layer thicknesses, ensuring the control gate surface is protected during etching while maintaining overall device functionality
2Reliability
If the BARC and photoresist layers are made thicker to protect the control gate, then surface damage is prevented, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
By forming the gate structure in the logic region first, the patent creates a protective foundation that allows standard-thickness BARC and photoresist layers to be applied later without risking control gate damage. This eliminates the need for excessively thick protective layers, maintaining manufacturing efficiency while ensuring surface protection
Solution Approach 2:
The gate structure formed in the logic region serves as a cushioning layer that protects the underlying structures during subsequent etching processes. This beforehand cushioning allows the use of standard-thickness BARC and photoresist layers, preventing the need for time-consuming thick layer deposition while still providing adequate protection
Data Source
AI summary
Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region. A gate dielectric material layer is formed to cover the first region, and a control gate dielectric layer is formed over a surface portion of the second region. The control gate dielectric layer has a top surface higher than the gate dielectric layer. A gate material layer is conformally formed to cover an entire surface of the semiconductor substrate and has a top surface in the second region higher than a top surface in the first region. A first filling material layer is formed on the gate material layer. A first patterned mask layer is formed on the first filling material layer to form a gate on a gate dielectric layer in the first region. A control gate is formed on the control gate dielectric layer of the second region.