Embedded Floating-Gate Flash Memory for Low-Profile SoC Integration
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Solution Overview
Problem
The integration of flash memories with different types of circuits in System-On-Chip technology faces challenges due to structural differences, leading to difficulties in embedding memory devices with other types of devices as technology evolves.
Innovation Solution
The formation of embedded flash memory devices involves embedding floating gates in a substrate, reducing the height of gate stacks by partially incorporating them into the substrate, and using a dual layer structure for the blocking layer to maintain charge retention and reduce threshold voltage mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gates are formed completely over the substrate, then charge storage capability is improved, but height discrepancy with other transistor gate stacks increases
Solution Approach 1:
The floating gate is embedded within the substrate, nesting the charge storage structure inside the substrate volume rather than extending above it. This allows the floating gate to maintain its charge storage function while being concealed within the substrate, reducing the overall gate stack height to match other transistors.
Solution Approach 2:
The floating gate structure transitions from a vertical extension above the substrate to a horizontal embedding within the substrate. By moving the floating gate into the substrate dimension, the patent achieves charge storage capability while maintaining a low profile that matches standard transistor gate stacks.
2Length of stationary object
If floating gates are embedded in the substrate, then height consistency with other transistors is improved, but charge retention capability may deteriorate
Solution Approach 1:
The substrate region containing the floating gate is selectively modified to provide enhanced charge retention properties. By applying different material compositions or structural characteristics locally at the floating gate embedding site, the patent ensures adequate charge retention while maintaining overall height consistency with other transistors.
3Reliability
If different blocking layer structures are used for flash memory and other circuits, then charge storage performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The blocking layer structure is designed to serve multiple functions: it blocks charge leakage while also providing mechanical support and electrical isolation for both flash memory cells and standard transistors. This universal blocking layer design enables a single manufacturing process to produce different device types without requiring separate specialized structures.
Data Source
AI summary
An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.