Substrate-Embedded Floating Gate Flash for SoC Integration
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Solution Overview
Problem
The integration of flash memories with different types of circuits in System-On-Chip technology faces challenges due to structural differences, leading to difficulties in embedding memory devices with other types of devices as technology evolves.
Innovation Solution
The formation of embedded flash memory devices involves embedding the floating gate in the substrate, reducing the height of the gate stacks and allowing for a dual layer blocking structure that maintains charge retention while reducing threshold voltage mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memories are integrated with other circuits in System-On-Chip technology, then device functionality and integration density are improved, but structural differences between flash memory and other circuit devices create manufacturing complexity and threshold voltage mismatches
Solution Approach 1:
The patent applies local quality by creating region-specific structures: flash memory cells have floating gates embedded in the substrate with extended blocking layers, while other circuit devices have standard gate structures. This allows each device type to have optimized local characteristics while maintaining overall integration on the same chip, resolving the contradiction between integration capability and manufacturing complexity.
Solution Approach 2:
The patent segments the chip into distinct functional regions with different device structures. Flash memory regions use substrate-embedded floating gates with dual-layer blocking structures, while other circuit regions use conventional transistors. This segmentation enables independent optimization of each device type while maintaining compatibility in the integrated system.
2Reliability
If floating gate is embedded in substrate with extended blocking layer, then charge retention is improved, but gate stack height increases causing CMP process difficulties
Solution Approach 1:
The patent resolves the height conflict by transitioning to a planar dimension solution. Instead of increasing vertical gate stack height, the blocking layer is extended laterally beyond the floating gate edges. This dimensional shift maintains charge retention through extended blocking while keeping the gate stack height compatible with standard CMP processes for other circuit devices.
Solution Approach 2:
The blocking layer is segmented into two functional zones: a vertical portion that provides charge blocking and a lateral extension portion that prevents charge leakage without increasing gate stack height. This segmentation allows the structure to achieve both reliable charge retention and CMP process compatibility.
3Reliability
If different device structures are used for flash memory and other circuits, then device-specific performance is optimized, but threshold voltage mismatches and manufacturing variability increase
Solution Approach 1:
The patent controls threshold voltage by adjusting the doping concentration and profile in the substrate region beneath the floating gate. By modifying substrate doping parameters rather than changing the fundamental device structure, the patent achieves distinct threshold voltage levels for flash memory cells while maintaining manufacturing compatibility with other circuit devices on the same chip.
Data Source
AI summary
An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.