Embedded FPGA Timing Sign-off Bypassing Interface Registers
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Solution Overview
Problem
The integration of a host ASIC with an embedded FPGA during sign-off checks is challenging due to the inability to precisely model paths that bypass interface cluster registers, leading to delays and potential computation errors, especially since these paths depend heavily on the place-and-route implementation.
Innovation Solution
The implementation of advanced timing modes that bypass interface cluster registers by using a timing budget to model delays, allowing for clock trunk inputs with internal or external divergence and boundary clock inputs, which reduce clock skew and on-chip variation, thereby avoiding the need for additional interface registers and minimizing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interface cluster registers are used to hold data values between host ASIC and integrated FPGA, then data transmission reliability is improved, but circuit complexity and delays increase
Solution Approach 1:
The patent extracts the timing analysis function from the physical circuit implementation by using a timing budget model. Instead of relying on interface cluster registers to manage timing, the invention creates a virtual timing model that predicts timing behavior without requiring additional physical registers or circuitry.
Solution Approach 2:
The patent changes the approach from physical circuit modification (adding registers) to parameter-based modeling (timing budget). The timing budget defines maximum delays for clock and data paths, allowing timing verification through parameter comparison rather than physical circuit analysis.
2Reliability
If interface cluster registers are added between host ASIC and integrated FPGA, then timing control is improved, but operation speed deteriorates due to additional delays
Solution Approach 1:
The timing budget acts as an intermediary that mediates between the host ASIC and integrated FPGA timing requirements. Instead of using physical registers as intermediaries, the timing budget provides a virtual mediation layer that defines acceptable timing parameters without introducing physical delays.
3Measurement precision
If static timing analysis is performed on integrated design, then timing verification is improved, but manufacturing precision requirements increase due to place-and-route dependencies
Solution Approach 1:
The patent performs preliminary timing analysis using the timing budget model before place-and-route implementation. By establishing maximum delay budgets in advance, the invention allows timing verification independent of the final physical layout, eliminating the need for iterative timing analysis after place-and-route.
Data Source
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AI summary
An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at the boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the ASIC boundary. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that the clock divergence occurs before the clock enters the embedded FPGA trunk. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.