Embedded Frame Electronic Package for Thermal Warpage Control
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Solution Overview
Problem
The challenge in semiconductor packaging is controlling warpage due to thermal expansion mismatches between chips and substrates, which becomes increasingly difficult as packages grow larger, and existing solutions like thicker encapsulation or larger metal frames either fail to effectively address warpage or increase package size and cost.
Innovation Solution
The proposed solution involves an electronic package design where an annular frame is embedded in the encapsulation layer but does not contact the substrate, helping to resist thermal stress and prevent warpage. This design allows for the arrangement of other electronic components without increasing the substrate size, thereby reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of encapsulation compound is increased to control warpage, then warpage control is improved, but package height increases and volume becomes larger
Solution Approach 1:
The solution divides the warpage control function into two parts: the encapsulation compound provides basic protection and filling, while a separate metal frame structure provides the primary warpage control. This segmentation allows the encapsulation thickness to remain thin while still achieving effective warpage control through the metal frame's high CTE and structural rigidity.
Solution Approach 2:
The patent uses a composite structure combining encapsulation compound and metal frame. The metal frame material is selected specifically for its high coefficient of thermal expansion (CTE) that compensates for the warpage caused by CTE mismatch between chip and substrate. This composite approach allows thin encapsulation while maintaining warpage control.
2Manufacturing precision
If a larger metal frame is used to control warpage, then warpage control is improved, but substrate size must be increased and cost increases
Solution Approach 1:
The metal frame is positioned specifically at the periphery of the substrate where it is most effective for warpage control. The frame's width, thickness, and CTE are optimized for this specific location and function, rather than requiring a uniformly large substrate. This localized approach allows effective warpage control with minimal substrate area.
Solution Approach 2:
The patent optimizes specific parameters of the metal frame including its width (1-5mm), thickness (0.1-1mm), and material CTE (10-20 ppm/°C) to achieve effective warpage control. By carefully controlling these parameters, the frame provides maximum warpage compensation with minimal substrate area requirement.
3Manufacturing precision
If a larger metal frame is used to control warpage, then warpage control is improved, but manufacturing cost increases
Solution Approach 1:
The metal frame can be manufactured as a separate component using stamping or molding processes, then transferred and positioned on the substrate. This copying approach allows standardized, cost-effective production of the frame structure independent of the substrate manufacturing process, reducing overall manufacturing cost while maintaining effective warpage control.
4Productivity
If the chip size to package size ratio is increased to accommodate more I/Os, then I/O capacity is improved, but warpage control becomes more difficult
Solution Approach 1:
The metal frame is designed with high CTE to preemptively counteract the warpage forces that will arise from the large chip-to-package ratio and CTE mismatch. By positioning the frame at the periphery and selecting appropriate material properties, the structure pre-compensates for thermal expansion differences, allowing high I/O capacity without sacrificing warpage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The frame effectively prevents warpage during thermal cycles, allowing for the placement of additional components without enlarging the substrate, thus reducing production costs and maintaining the lightweight, thin, and short form factor required for modern electronic products.
Implementation Method 1
the coefficient of thermal expansion (CTE) of the chip is too different from the CTE of the substrate... causing the warpage of the package to become difficult to control
Implementation Method 2
the frame is embedded in the encapsulation layer and located on a periphery of the substrate and free from being in contact with the substrate... the frame effectively prevents warpage during thermal cycles
Data Source
AI summary
The present disclosure discloses an electronic package and a manufacturing method thereof. An electronic component is disposed on a substrate, an encapsulation layer covers the electronic component, and a frame that is not in contact with the substrate is embedded in the encapsulation layer, thereby preventing the electronic package from warping by the frame resisting thermal stress.