Embedded GaN Die Packaging With Dual-Side Cooling for Thermal Limits
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Solution Overview
Problem
Current embedded die packaging for high voltage/high current power semiconductor devices, such as GaN HEMTs, faces challenges in thermal management and reliability due to limited thermal pad area and parasitic inductance, which restricts performance and reliability at elevated temperatures.
Innovation Solution
The implementation of dual-side-cooled embedded die packaging, where a primary thermal pad is provided on one side and a secondary thermal pad on the opposite side, utilizing a laminated body with dielectric and conductive layers to enhance thermal dissipation and reduce thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-side cooled package is used, then the package structure is simple, but the thermal resistance is high and thermal management is limited
Solution Approach 1:
The patent transitions from single-side cooling to dual-side cooling by adding thermal dissipation in the vertical dimension (both top and bottom surfaces), effectively utilizing three-dimensional thermal pathways to reduce thermal resistance without proportionally increasing package footprint area
Solution Approach 2:
The package is segmented into multiple functional layers including first and second thermal pads, conductive layers, and dielectric layers, allowing independent optimization of thermal and electrical pathways on each side of the device
2Temperature
If the thermal pad area is increased, then thermal dissipation is improved, but the parasitic inductance increases and power density decreases
Solution Approach 1:
Different regions of the package are assigned different functions: thermal pads are optimized for heat dissipation while conductive layers are optimized for electrical connectivity, allowing each region to be locally optimized for its specific purpose without compromising overall performance
Solution Approach 2:
The patent utilizes vertical layering to separate thermal and electrical functions into different dimensional planes, with thermal pads on the surface and conductive layers embedded within the substrate, reducing parasitic inductance by shortening current paths
3Power
If a smaller die size is used, then power density is improved, but thermal management becomes more challenging due to limited thermal pad area
Solution Approach 1:
By implementing dual-side cooling, the patent effectively doubles the thermal dissipation area available for a given die size, allowing smaller high-power-density devices to be cooled efficiently without requiring proportionally larger package footprints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces thermal resistance by up to 40% compared to conventional single-side cooled packages, enabling improved reliability and power density, and mitigates the limitations of thermal pad area and parasitic inductance.
Implementation Method 1
the first and second thermal pads providing for dual-side cooling
Data Source
AI summary
Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers, and wherein a first thermal pad on one side of the package and a second thermal pad on an opposite side of the package provides for dual-side cooling. Example embodiments of the dual-side cooled package may be based on a bottom-side cooled layup with a primary bottom-side thermal pad and a secondary top-side thermal pad, or a top-side cooled layup with primary top-side thermal pad and a secondary bottom side thermal pad, using layups with or without a leadframe. For example, the power semiconductor switching device comprises a GaN power transistor, such as a GaN HEMT rated for operation at ≥100V or ≥600V, for switching tens or hundreds of Amps.