Embedded GaN HEMT Structure for Higher Breakdown and Lower ROn

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Solution Overview

Problem

High electron mobility transistors (HEMTs) face challenges in increasing breakdown voltage and reducing on-state resistance while maintaining device thickness and functionality, particularly with GaN-based materials used in high power and high frequency applications.

Innovation Solution

The HEMT structure incorporates a substrate with a first III-V compound layer and a second III-V compound layer embedded within it, featuring a P-type gallium nitride gate and electrodes, where the second III-V compound layer is formed using epitaxial processes like MOCVD or MBE, allowing for enhanced breakdown voltage and reduced on-state resistance without increasing the total device thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the total thickness of the HEMT is increased to improve breakdown voltage, then breakdown voltage is improved, but device thickness increases which is not desirable

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent embeds a second III-V compound layer within a first III-V compound layer, creating a nested structure where the gate electrode is positioned within the embedded layer. This nesting approach allows the electric field to be better controlled and distributed, improving breakdown voltage without requiring an increase in overall device thickness. The embedded configuration enables the structure to achieve higher reliability while maintaining compact dimensions.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the on-state resistance is reduced by modifying the structure, then on-state resistance is improved, but device complexity increases

Engineering Contradiction:
Improveon-state resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs different III-V compound materials with distinct compositions in different regions of the device. The first III-V compound layer has a different composition than the second embedded III-V compound layer, allowing each region to be optimized for specific functions. This local differentiation enables reduced on-state resistance in the channel region while maintaining overall structural manageability through systematic material selection rather than random complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively increases breakdown voltage and reduces on-state resistance while maintaining the device's thickness, enabling improved performance in high power and high frequency applications by generating a trench profile two-dimensional electron gas for efficient carrier switching.

Implementation Method 1

A two-dimensional electron gas (2DEG) may be generated by the piezoelectric property of the GaN-based materials

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Implementation Method 2

A first epitaxial process is performed to form a second III-V compound layer filling up the first trench. Later, the second III-V compound layer is etched to form a second trench. A second epitaxial process is performed to form a P-type gallium nitride gate filling up the second trench

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12057490B2High electron mobility transistor structure and method of fabricating the same
Publication Date: 2024.08.06 UNITED MICROELECTRONICS CORP
  • US12057490B2 patent drawing
  • US12057490B2 patent drawing
  • US12057490B2 patent drawing

AI summary

A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.