Embedded Gate Electrodes in Trenches for Vertical Transistors
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Solution Overview
Problem
The miniaturization of semiconductor devices, particularly vertical transistors, leads to increased production costs due to the need for separate steps in forming semiconductor pillars and gate electrodes, resulting in non-uniformity and reduced semiconductor characteristics.
Innovation Solution
A semiconductor device design featuring embedded gate electrodes in trenches within a semiconductor substrate, allowing for simultaneous formation of peripheral and memory cell regions, reducing the number of production steps and eliminating the need for whole-surface etching, thereby improving transistor characteristics and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate steps are provided for forming semiconductor pillars and memory cell regions, then vertical transistors can be formed in peripheral circuit regions, but production costs markedly increase
Solution Approach 1:
The patent merges the formation steps of semiconductor pillars and memory cell regions into a single integrated process. Trenches are formed simultaneously in both regions, and gate electrodes are formed in both regions during the same manufacturing sequence, eliminating the need for separate processing steps and reducing production costs
2Ease of operation
If whole-surface etching is performed to form gate electrodes, then gate electrodes can be formed on side surfaces of semiconductor pillars, but uniformity of etching back becomes difficult to control
Solution Approach 1:
The patent segments the gate electrode formation process into localized trench etching followed by selective gate electrode deposition only in the trench regions. This avoids whole-surface etching and enables precise control of gate electrode height and uniformity by confining the etching and deposition processes to specific localized areas
3Reliability
If miniaturization is pursued to achieve fully depleted semiconductor devices, then device performance improves, but the need for separate processing steps increases production complexity
Solution Approach 1:
The patent combines multiple miniaturization-enabling features into a single integrated structure: narrow trenches form both the semiconductor pillars and the gate electrodes simultaneously, achieving fully depleted characteristics while reducing processing complexity through unified formation steps
Data Source
AI summary
One semiconductor device includes first to third gate electrodes arranged inside a first active region and embedded in first to third trenches extending in a first direction, a first semiconductor pillar positioned between the first and second trenches, a second semiconductor pillar positioned between the second and third trenches, a first vertical transistor having the first and second gate electrodes as the double gate electrodes therefor, and a second vertical transistor having the second and third gate electrodes as the double gate electrodes therefor. The second gate electrode is shared by the first vertical transistor and the second vertical transistor.