Embedded Gate Structure for Leakage-Controlled Semiconductor Fabrication
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Solution Overview
Problem
As semiconductor devices shrink in size, leakage current increases, and integrating devices with different driving voltages on the same chip poses process control challenges due to varying gate dielectric layer thicknesses.
Innovation Solution
A semiconductor device design featuring a gate structure embedded in a substrate with an insulating layer encompassing the gate structure, along with source/drain regions, to manage leakage current and process control issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices is reduced, then production cost is reduced and competitive advantage is improved, but leakage current increases
Solution Approach 1:
The gate structure is divided into two parts: a first gate structure extending above the substrate and a second gate structure embedded in the substrate. This segmentation allows different regions to serve different functions - the first gate for primary control and the second gate for suppressing leakage current through electrostatic control of the channel region beneath it.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the second gate structure and the substrate. This insulating layer enables the second gate to electrostatically control the channel region without direct electrical connection to the substrate, effectively suppressing leakage current while maintaining device functionality.
2Adaptability or versatility
If devices with different driving voltages are integrally formed in a same chip, then product versatility is improved, but process control difficulty increases due to varying gate dielectric layer thicknesses
Solution Approach 1:
Different gate structures are employed in different regions of the chip to match local voltage requirements. Low-voltage devices use a standard thin gate dielectric layer, while high-voltage devices use a thicker gate dielectric layer with an embedded gate structure. This local differentiation allows each region to be optimized for its specific voltage requirement without compromising the entire chip's process control.
Solution Approach 2:
The chip is segmented into different device regions with different gate structures. The embedded second gate structure in high-voltage regions provides additional electrostatic control that compensates for the thicker gate dielectric, enabling high-voltage operation while maintaining manufacturing compatibility with standard CMOS processes.
3Reliability
If a thicker gate dielectric layer is used to sustain higher operation voltage, then voltage sustainment is improved, but gate height becomes different from other devices which increases process control difficulty
Solution Approach 1:
Instead of only varying gate dielectric thickness in the vertical dimension, the invention adds a horizontal dimension by introducing a second gate structure embedded in the substrate. This additional gate provides electrostatic control from below, compensating for the reduced field effect of the thicker gate dielectric and enabling high-voltage operation without compromising process control.
Solution Approach 2:
The insulating layer acts as an intermediary that allows the embedded second gate to control the channel region electrostatically without direct contact. This enables the thicker gate dielectric to sustain higher voltages while the embedded gate maintains proper electrostatic control, resolving the conflict between voltage sustainment and process control.
Data Source
AI summary
A semiconductor device includes a gate structure, an insulating layer and two source/drain regions. A portion of the gate structure is embedded in a substrate. The insulating layer is disposed between the portion of the gate structure and the substrate and encompasses the portion of the gate structure. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure.