Embedded Gate Non-Volatile Memory Cell Design
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Solution Overview
Problem
There is a constant need for reducing the size of memory cells in non-volatile memory devices while maintaining their functionality and efficiency.
Innovation Solution
A compact memory cell design is proposed, featuring a selection transistor with an insulated selection gate embedded in a semiconducting substrate region, a floating gate partially embedded above the selection gate, and a control gate insulated from the floating gate, allowing for reduced surface area and programmability through the Fowler-Nordheim effect and Source Side Injection (SSI) techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional memory cell design is used, then functionality and efficiency are maintained, but surface area is large
Solution Approach 1:
The patent implements nested transistor structures where the state transistor is embedded within the selection transistor structure. The floating gate of the state transistor is positioned above the embedded selection gate, creating a vertically stacked configuration that reduces lateral footprint while maintaining both transistor functionalities
Solution Approach 2:
The patent transitions from planar transistor layout to vertical stacking by embedding gates within the substrate and positioning floating gates above them. This three-dimensional arrangement reduces the surface area occupied by each memory cell while preserving the electrical functionality of both selection and state transistors
2Area of moving object
If memory cell size is reduced, then surface area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory cell into distinct functional segments: the embedded selection gate within the substrate, the floating gate positioned above it, the control gate insulated from the floating gate, and the source/drain regions. This segmentation allows each component to be precisely positioned and manufactured independently, reducing overall complexity despite the compact footprint
3Area of moving object
If embedded transistor structure is used, then surface area is reduced, but access resistance to source areas increases
Solution Approach 1:
The patent optimizes the local electrical properties of the source region by ensuring it remains accessible from the surface while the gates are embedded. The source region is positioned to maintain low-resistance contact paths, compensating for the embedded gate structure and preventing increased access resistance despite the reduced surface footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the creation of smaller memory cells with reduced surface area, allowing for efficient programming, erasure, and reading, while minimizing the resistance of access to the source areas, thus addressing the need for compact memory solutions.
Implementation Method 1
This memory cell is advantageously erasable by the Fowler-Nordheim effect
Implementation Method 2
programmable by injection of hot carriers on the source side, a phenomenon known to those skilled in the art by the acronym SSI ('Source Side Injection')
Data Source
AI summary
A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.