Embedded Gate Recess Structure for DRAM Sneak Current Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with embedded word lines, charges can move upwardly or laterally, affecting the reliability of transistors and dynamic random access memory (DRAM) by increasing parasitic capacitance and leading to sneak currents and interference with adjacent devices.
Innovation Solution
A manufacturing method that forms a recess in the substrate, where a channel layer and barrier layer induce a heterojunction external to the substrate, allowing for the formation of a conductive channel within the recess, reducing charge movement to drain or source electrodes and adjacent devices, and includes a hard mask pattern to block further charge interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the conductive channel is formed close to the sidewall of the recess in the substrate, then the integration level of DRAM is improved and parasitic capacitance between word lines and bit lines is reduced, but charges move upwardly or laterally causing sneak currents and reducing device reliability
Solution Approach 1:
The conductive channel is repositioned from a lateral position close to the recess sidewall to a vertical position within the recess, utilizing the depth dimension of the substrate. This dimensional shift allows the channel to be embedded deeper, isolating charges from lateral movement paths while maintaining high integration density through vertical stacking of device components.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the conductive channel and the substrate surface. This insulating barrier prevents charge carriers from moving upwardly from the channel to the substrate, blocking the sneak current path while allowing the channel to maintain its electrical function. The insulating layer acts as a mediator that decouples the channel from harmful charge leakage paths.
2Ease of operation
If charges are allowed to move freely in the substrate, then device operation is simplified, but sneak currents increase and interfere with adjacent memory cells
Solution Approach 1:
The conductive channel is extracted from the substrate surface region and embedded within the recess, removing it from the region where lateral charge movement occurs. This extraction isolates the channel from the substrate's charge leakage paths, preventing sneak currents from forming while maintaining the channel's electrical conductivity for normal device operation.
Solution Approach 2:
Insulating structures are formed in advance around and above the conductive channel to create preliminary barriers against charge movement. These pre-formed insulating layers prevent charges from moving laterally or upwardly before sneak currents can develop, proactively blocking harmful charge leakage paths while allowing normal device operation to proceed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability of semiconductor devices by preventing sneak currents and reducing interference with adjacent devices, improving the integration level and performance of DRAM with embedded word lines.
Implementation Method 1
a hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate
Data Source
AI summary
A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.