Embedded Gateway Data Prefetch for DRAM Stall Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional network processing units (NPUs) experience significant stalling times due to long data access operations on external memories like DRAM, leading to inefficient use of processor resources.
Innovation Solution
An embedded gateway system with a data prefetch circuit that proactively reads data from a low-speed memory and writes it to a high-speed memory before the processor needs it, reducing stalling time by utilizing a RISC-V processor, a first memory, and a second memory with lower access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory (DRAM) is used to store packet data for the RISC-V processor, then data storage capacity is improved, but data access latency increases causing processor stalling
Solution Approach 1:
The memory system is segmented into two distinct memory components: a first external memory (DRAM) for bulk data storage and a second external memory for fast data access. This segmentation allows the system to maintain both large storage capacity and fast access speed by dividing the memory functionality across two specialized memory types.
Solution Approach 2:
The data prefetch circuit performs preliminary actions by proactively reading data from the first external memory and pre-loading it into the second external memory before the processor actually needs to access it. This preliminary data transfer operation ensures that when the processor requires the data, it is already available in the fast memory, eliminating stalling time.
2Reliability
If the processor waits for data access operation on DRAM to complete, then data access accuracy is ensured, but processor resource utilization decreases
Solution Approach 1:
The data prefetch circuit acts as an intermediary component between the processor and the external memory system. It handles the data transfer operations from the first external memory to the second external memory, allowing the processor to continue executing other instructions without waiting for data access operations to complete, thus maintaining both data accuracy and high processor utilization.
Solution Approach 2:
The system enables continuous useful action by overlapping the data prefetch operation with processor execution. While the data prefetch circuit is transferring data in the background, the processor continues to execute other instructions without interruption. This ensures that the processor remains productive and does not stall waiting for memory operations to complete.
Data Source
AI summary
An embedded gateway system includes a processor, a first memory, a second memory, and a data prefetch circuit. The processor is used to execute a first program. The first memory is used to store a first data. The first memory and the second memory are external memories of the processor, and access latency of the second memory is lower that access latency of the first memory. The data prefetch circuit is used to perform a first data prefetch operation upon the first memory for reading a first prefetched data from the first memory and writing the first prefetched data into the second memory. Before a time point at which the processor executes a data access code segment of the first program to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetched data.