Embedded Gettering Layer Structure for Low-Contamination SOI Wafers

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Solution Overview

Problem

Metal contamination in silicon on insulator (SOI) substrates leads to crystal defects, junction leakage, and insulation breakdown, affecting the electrical properties and reliability of semiconductor devices.

Innovation Solution

A gettering layer is interposed between the epitaxial silicon layer and the buried oxide layer to trap and remove metal impurities, using materials like silicon, silicon germanium, silicon nitride, or silicon oxynitride, deposited through methods such as CVD, to enhance metal gettering ability and reduce contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a gettering layer is added between the epitaxial silicon layer and the buried oxide layer, then metal contamination is reduced, but the device structure becomes more complex

Engineering Contradiction:
Improvemetal contamination reductionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gettering layer is nested within the existing SOI structure, specifically positioned between the epitaxial silicon layer and the buried oxide layer. This integration approach allows the gettering function to be incorporated without adding external components, thus reducing the overall structural complexity while maintaining the metal contamination reduction benefit

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The gettering layer serves multiple functions: it acts as a metal trap to capture contaminant atoms, provides an additional interface for defect management, and maintains electrical isolation properties. This multi-functionality allows a single layer to address multiple reliability concerns simultaneously, justifying its inclusion despite the increased structural complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a gettering layer is deposited using CVD or other methods, then metal gettering ability is enhanced, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvemetal gettering abilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The gettering layer deposition is merged with the existing epitaxial growth or dielectric deposition processes already present in the SOI manufacturing flow. By using standard CVD equipment and integrating the gettering layer formation into existing process steps, the additional manufacturing complexity is minimized while still achieving enhanced metal gettering ability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The deposition parameters (temperature, pressure, gas flow rates) are optimized to achieve the desired gettering performance within the existing process window. By adjusting these parameters rather than introducing entirely new process steps, the manufacturing complexity is reduced while maintaining effective metal contamination control

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The embedded gettering layer effectively reduces metal contamination to levels below 1×10^9 atoms/cm², improves device reliability, and allows for lower thermal budgets in manufacturing, eliminating bulk micro defects and enhancing metal gettering proximity to device fabrication regions.

Implementation Method 1

A gettering layer is interposed between the epitaxial silicon layer and the buried oxide layer to trap and remove metal impurities

Methodology Applied
Scientific EffectAdsorption: Adsorption

Implementation Method 2

using materials like silicon, silicon germanium, silicon nitride, or silicon oxynitride, deposited through methods such as CVD

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS12387943B2Structure for embedded gettering in a silicon on insulator wafer
Publication Date: 2025.08.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12387943B2 patent drawing
  • US12387943B2 patent drawing
  • US12387943B2 patent drawing

AI summary

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.