Embedded Harmonic Termination for High Power RF Transistors
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Solution Overview
Problem
Conventional harmonic tuning designs for Class F RF amplifiers face challenges in effectively filtering higher order harmonics due to parasitic reactance of package and board level conductors, limiting the ability to tune out harmonics, especially at higher frequencies like 6 GHz.
Innovation Solution
Incorporating harmonic filtering structures directly into the back end of the line metallization of the integrated circuit, using a coplanar waveguide configuration with interdigitated elongated fingers and patterned shapes in the metallization layer to provide a non-linear impedance response tuned to the fundamental frequency, effectively filtering harmonic components by disrupting the ground plane and minimizing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional harmonic tuning designs use external filters and impedance matching networks on PCB or package level, then harmonic filtering can be achieved, but parasitic reactance of conductors substantially influences higher frequency signals and limits tuning effectiveness
Solution Approach 1:
The patent combines the harmonic filtering function directly into the back end of the line metallization structure of the semiconductor device, merging the amplifier device and filtering structures into a single integrated unit. This eliminates the need for separate external filters and impedance matching networks, thereby removing the parasitic reactance introduced by package and board level conductors and enabling effective harmonic filtering at higher frequencies.
2Reliability
If higher order harmonics are filtered using external LC filters or microstripline geometries on PCB, then some harmonic suppression is achieved, but the ability to tune out harmonics becomes increasingly difficult with increasing separation from the current source
Solution Approach 1:
The filtering structures are merged into the back end of the line metallization of the integrated circuit, creating a compact integrated solution that provides both harmonic suppression and impedance matching functions within the semiconductor device itself, eliminating the need for complex external filtering components.
Solution Approach 2:
The patent implements different geometric patterns in different regions of the back end of the line metallization to provide frequency-dependent impedance characteristics. Specific patterned shapes are placed at strategic locations to create resonant circuits that present specific impedances to different harmonic frequencies, enabling effective tuning of multiple harmonics simultaneously.
3Loss of energy
If Class F amplifier operation is implemented to achieve high efficiency, then power dissipation is minimized during ON and OFF states, but power dissipation occurs during transition between states when current and voltage overlap
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the back end of the line metallization with filtering structures that anticipate and counteract the harmonic content generated during transistor switching transitions. The filtering structures are designed to present appropriate impedances to harmonic frequencies before they can cause excessive current-voltage overlap, thereby reducing transition losses and improving overall amplifier efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves excellent harmonic filtering performance with minimal parasitic effects, providing a low-cost and simple solution by ensuring minimal impedance to second-order harmonics and maximal impedance to third-order harmonics, thereby enhancing the efficiency of Class F amplifier operation.
Implementation Method 1
The first patterned shape has a geometry that filters harmonic components of the fundamental frequency
Implementation Method 2
parasitic reactance of the package level and board level conductors substantially influences the propagation of higher frequency signals
Data Source
AI summary
A semiconductor includes a semiconductor substrate having first and second opposite facing surfaces. An amplifier device is formed in the semiconductor substrate, the amplifier device is configured to amplify an RF signal at a fundamental frequency. A first dielectric layer is formed on the first surface of the substrate. A first metallization layer is formed on the first dielectric layer. The first metallization layer is spaced apart from the substrate by the first dielectric layer. The first metallization layer includes a first elongated finger interdigitated with a first reference potential pad. The first elongated finger is physically disconnected from the first reference potential pad. The first reference potential pad includes a first patterned shape that is devoid of metallization. The first patterned shape has a geometry that filters harmonic components of the fundamental frequency.