Embedded Heat Dissipation Feature for 3DIC Thermal Management

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Solution Overview

Problem

Three-dimensional integrated circuits (3DICs) face heat dissipation challenges, particularly with the bottom die experiencing high thermal resistance and excessive temperature rise due to heat generated by stacked components, which can reduce reliability and operating lifetime, especially in high-power components like CPUs.

Innovation Solution

The integration of an embedded heat dissipation feature (eHDF) within the package structure, utilizing high thermal conductivity materials and adhesives, provides additional heat dissipation pathways from the chips to the substrate and a heat sink, bypassing the top die, thereby improving thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a heat sink is mounted on the top die for heat dissipation, then the top die experiences good heat-dissipating condition, but the bottom die suffers from heat-dissipation problem due to high thermal resistance of the top die

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidbottom die temperature control
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent transitions from single-point top-side cooling to a distributed three-dimensional cooling architecture. Multiple heat dissipation pathways are created by embedding heat dissipation features at different vertical levels (between dies and at substrate level), transforming the cooling approach from two-dimensional surface cooling to three-dimensional volumetric cooling that addresses heat sources throughout the stack.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The heat dissipation function is segmented into multiple independent heat dissipation features distributed throughout the 3DIC stack. Instead of relying on a single heat sink at the top, the patent divides the thermal management system into multiple segments: heat dissipation features embedded between individual dies and additional features at the substrate level, allowing each segment to independently manage heat from specific dies.

Inventive Principle:
Principle #1Segmentation

2Productivity

If integration density is increased by stacking dies, then footprint is reduced and power consumption decreases, but heat dissipation becomes more difficult due to thermal resistance accumulation

Engineering Contradiction:
Improveintegration densityVSAvoidthermal resistance
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent addresses thermal resistance in stacked configurations by introducing vertical heat dissipation pathways at multiple levels within the three-dimensional stack. Heat dissipation features are embedded between dies at different vertical positions and at the substrate level, creating a multi-level thermal management architecture that efficiently manages heat from high-density stacked dies without increasing footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces the thermal resistance and prevents excessive temperature rise in 3DICs, enhancing the reliability and operational lifespan of high-power components by providing direct and efficient heat dissipation paths.

Implementation Method 1

utilizing high thermal conductivity materials and adhesives, provides additional heat dissipation pathways from the chips to the substrate and a heat sink

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

heat sink may be mounted on the top die. As a result, the top die may experience good heat-dissipating condition through natural convection with ambient air flow or with forced convection by utilizing a fan

Methodology Applied
Scientific EffectConvection: Convection

Data Source

PatentUS11133237B2Package with embedded heat dissipation features
Publication Date: 2021.09.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11133237B2 patent drawing
  • US11133237B2 patent drawing
  • US11133237B2 patent drawing

AI summary

An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.