Embedded High-Speed Protocol for Distributed Control Systems

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Solution Overview

Problem

Current distributed embedded control systems face challenges in choosing a communication protocol that balances bandwidth, latency, and synchronization requirements, with existing protocols like CANFD being non-backward compatible and requiring precise clocks, leading to implementation difficulties and high costs in industries like automotive.

Innovation Solution

Embedding a second high-speed protocol within a first protocol, allowing modules to operate seamlessly with both protocols without disturbing existing systems, enabling gradual upgrades and increased bandwidth without requiring all modules to be replaced.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a high-speed protocol like CANFD is adopted, then bandwidth and communication speed are improved, but backward compatibility is lost and implementation complexity increases

Engineering Contradiction:
Improvecommunication speedVSAvoidbackward compatibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent embeds the high-speed CANFD protocol within the existing CAN protocol framework. CANFD messages are encapsulated as CAN messages, allowing the high-speed protocol to operate within the legacy protocol's message structure and timing constraints, thus maintaining backward compatibility while enabling high-speed communication

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent introduces an intermediary layer that translates between CAN and CANFD protocols. This intermediary enables gradual migration by allowing legacy CAN nodes to communicate with CANFD nodes through protocol conversion, bridging the compatibility gap without requiring complete system replacement

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If precise clock synchronization is implemented, then timing accuracy is improved, but device complexity and cost increase

Engineering Contradiction:
Improvetiming accuracyVSAvoidclock synchronization complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs self-service synchronization where nodes automatically adjust their timing based on received messages without requiring external synchronization infrastructure. The protocol includes built-in timing reference messages that nodes use to autonomously synchronize their clocks, eliminating the need for complex external clock distribution systems

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements feedback-based timing adjustment where nodes monitor message arrival times and automatically adjust their local clocks to compensate for drift. This closed-loop synchronization mechanism maintains timing accuracy using simple clock adjustments rather than complex synchronization hardware

Inventive Principle:
Principle #23Feedback

3Productivity

If all modules are upgraded to support high-speed protocol, then system performance is improved, but implementation cost and disruption increase

Engineering Contradiction:
Improvesystem performanceVSAvoidimplementation cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent segments the system into legacy CAN nodes and new CANFD nodes that can coexist on the same network. The high-speed protocol is activated only in segments where both ends support it, allowing incremental adoption without requiring complete system replacement. This segmentation enables performance improvement in specific communication paths while leaving other parts of the system unchanged

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11804919B2High speed embedded protocol for distributed control system
Publication Date: 2023.10.31 KVASER
  • US11804919B2 patent drawing
  • US11804919B2 patent drawing
  • US11804919B2 patent drawing

AI summary

Two or more modules communicate over a common control network including receiving by a message packet having data defined by a signal level at defined bit quanta of a bit, the defined bit quanta being less than every bit quanta of a bit, and the communication device samples bit quanta other than the defined bit quanta. The module receives signal disturbances and decodes the signal disturbances as having a value different from an expected value of the certain bit. In another form, the module uses a first counter based on a clock local to the communication device and a second counter having a higher sampling rate than the first counter. Here, the module receives over the control network a synchronizing portion of a message and counts clock ticks of the second counter over a portion of the message to determine a clock rate for a module that transmitted the message.