Embedded HV Gate Electrode Mitigates CMP Damage in Flash Memory Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, the integration of flash memory devices and high voltage (HV) devices into a common structure poses challenges such as gate damage and height loss during the chemical mechanical polish (CMP) process, particularly in high-k metal gate (HKMG) devices, due to the recessed regions required for HV devices.
Innovation Solution
The formation of shallow trenches and embedding the HV gate electrode within a dielectric trench liner in the semiconductor substrate, which mitigates gate damage by allowing the CMP process to occur without damaging the HV gate electrode, and facilitates the formation of suitable gate structures and isolation dielectrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flash memory devices and high voltage devices are integrated into a common semiconductor structure, then manufacturing cost is reduced and operational speed is increased, but gate damage and height loss occur during the CMP process
Solution Approach 1:
The semiconductor substrate is divided into a first region for flash memory devices and a second region for high voltage devices. This segmentation allows different device types to coexist in the same structure while maintaining their respective requirements, enabling integrated manufacturing without compromising gate electrode integrity in either region.
Solution Approach 2:
A gate protection layer is introduced as an intermediary element between the gate electrode and the CMP process. This protection layer prevents direct contact between the CMP slurry and the gate electrode surface, thereby preventing gate damage and height loss while allowing the CMP process to proceed for planarizing other structures.
2Manufacturing precision
If the CMP process is performed to planarize the semiconductor structure, then manufacturing precision is improved, but gate height loss and damage occur
Solution Approach 1:
The gate protection layer is formed on the gate electrode surface before the CMP process begins. This preliminary action ensures that the gate electrode is already protected when the CMP process starts, allowing the planarization to proceed without subsequent gate damage or height loss concerns.
Solution Approach 2:
The gate protection layer serves as a mediator that allows the CMP process to achieve surface planarity while simultaneously protecting the gate electrode. The protection layer absorbs the mechanical action of the CMP process, preventing it from directly affecting the gate electrode dimensions.
3Adaptability or versatility
If recessed regions are created for high voltage devices, then device integration is enabled, but gate damage during CMP process increases
Solution Approach 1:
The substrate is segmented into distinct first and second regions, with the second region containing recessed structures for high voltage devices. This segmentation allows the recessed regions to be created for device integration while the gate protection layer ensures that gate electrodes in both regions are protected during CMP processing.
Solution Approach 2:
The gate protection layer acts as an intermediary that shields gate electrodes from the harmful effects of the CMP process, particularly in regions with recessed structures where gate electrodes may be more vulnerable. The protection layer enables the CMP process to proceed safely across the entire substrate.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode and source and drain regions. The gate dielectric layer extends into a first trench in the semiconductor substrate. The gate electrode is over the gate dielectric layer and is at least partially embedded in the first trench in the semiconductor substrate. The source and drain regions are in the semiconductor substrate and proximate the first trench in the semiconductor substrate.