Embedded IC Package with Substrate Vias
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Solution Overview
Problem
Existing integrated circuit package technologies face challenges in reducing package dimensions, increasing manufacturing costs, and decreasing yields due to the need for additional space and complex processes, especially when stacking multiple integrated circuits or embedding them in printed circuit boards, which often result in damage to the integrated circuits.
Innovation Solution
The method involves forming a conductive pattern on a substrate, directly connecting an integrated circuit die with bumps to this pattern, encapsulating both in a low coefficient of thermal expansion (CTE) substrate forming encapsulation, and creating channels for conductive material application, which allows for ultra-thin integrated circuit embedding with reduced height and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple integrated circuits are stacked or embedded in printed circuit boards, then integration density increases, but package height reduction is limited and manufacturing complexity increases
Solution Approach 1:
The patent merges the substrate and encapsulation into a single integrated structure formed from a low CTE substrate material. The conductive patterns are formed directly on the substrate, and the encapsulation is created by forming voids and filling them with encapsulant material, eliminating the need for separate substrate and encapsulation components. This integration reduces manufacturing steps and complexity while maintaining high integration density.
Solution Approach 2:
The patent transitions from conventional planar packaging to a three-dimensional embedded structure. Integrated circuit dice are embedded within the substrate at different depths and positions, with conductive vias providing vertical interconnections. This dimensional change allows higher integration density without proportionally increasing package footprint or height.
2Reliability
If spacers or interposers are used to connect stacked integrated circuits, then electrical connections are established, but additional manufacturing steps and structures are required increasing cost and reducing yields
Solution Approach 1:
The patent extracts and eliminates the spacer or interposer component from the package structure. Instead of using separate spacer materials to establish electrical connections between stacked integrated circuits, the invention uses direct bonding techniques where the substrate itself provides the connection medium through formed conductive patterns and vias, reducing manufacturing steps and improving yields.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support, establishes electrical connections through conductive patterns, provides encapsulation when voids are filled, and enables thermal management. This multi-functionality eliminates the need for separate spacer or interposer components, reducing manufacturing complexity and cost.
3Quantity of substance
If conventional packaging technologies are used to integrate more functions, then functional integration increases, but package dimensions are not reduced
Solution Approach 1:
The patent implements a nested structure where integrated circuit dice are embedded within the substrate at different levels and positions. The substrate itself is formed with voids that are filled with encapsulant material, creating a nested configuration. This allows multiple functional elements to be packed into a smaller volume, reducing overall package dimensions while maintaining high functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of an embedded integrated circuit package system that reduces package height, simplifies manufacturing, minimizes damage to integrated circuits, and lowers overall system costs while maintaining performance by using a low CTE encapsulant and conductive vias for efficient signal transmission.
Implementation Method 1
forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern
Data Source
AI summary
A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.