Embedded IC-to-PCB Connection Using Photoablated Dielectric Cavities

The patent applies preliminary action by pre-forming catalyst patterns on the IC surface before embedding the IC in the substrate. This preliminary catalyst layer is then used to grow conductive pathways directly to the IC, eliminating the need for subsequent via formation and plating steps. The catalyst pattern is created using photoablation of photoimageable dielectric material, which allows precise positioning of conductive connections before the IC is permanently embedded.

The patent replaces traditional mechanical drilling and plating processes with a chemical deposition approach. Instead of mechanically forming vias and electroplating conductors, the invention uses photoablation to create catalyst patterns followed by electroless plating that grows conductive material directly along the catalyst pattern. This substitution simplifies the manufacturing process while improving IC connectivity.

The patent merges multiple functions into the photoablation process. The same photoablation technique used to define catalyst patterns is also used to create the embedding cavities for the IC. Additionally, the catalyst pattern formation and conductor growth are combined into a single electroless plating step that simultaneously creates both the catalyst pattern and the conductive pathway, reducing the total number of discrete processing steps.

The photoimageable dielectric material serves multiple functions: it acts as the embedding medium for the IC, provides the matrix for catalyst pattern formation through photoablation, and serves as the base layer for subsequent dielectric layers. This multi-functionality reduces the need for separate materials and processing steps for each function.

The patent replaces complex mechanical drilling, cleaning, and electroplating operations with a streamlined chemical process. Electroless plating is used to deposit conductor material directly onto the catalyst pattern, creating conductive pathways that automatically conform to the IC packaging geometry. This chemical approach eliminates the need for precise mechanical alignment and multiple plating steps required in conventional via formation.

The electroless plating process is self-aligning and self-conforming. The catalyst pattern automatically defines the conductor trajectory, and the plating process follows the catalyst pattern without requiring external alignment fixtures or complex process control. The conductor material deposits only where catalyst is present, automatically creating the correct connection geometry to the IC pads.