Embedded High-Voltage IMD Structure for 8V TDDB Reliability
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Solution Overview
Problem
The reduction in thickness of low-k or ultra-low-k inter-metal dielectric layers in embedded high-voltage semiconductor devices leads to failure in 8V TDDB reliability tests, causing inter-metal dielectric layer breakdown.
Innovation Solution
The implementation of a denser second inter-metal dielectric layer and the use of ultra-low dielectric constant materials, such as TEOS-based oxide or high-density plasma oxide, in combination with metal gates and tungsten contacts, along with specific manufacturing processes to form an embedded high-voltage semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of low-k or ultra-low-k inter-metal dielectric layer is reduced, then RC delay is reduced, but the embedded high-voltage device fails 8V TDDB reliability test due to dielectric breakdown
Solution Approach 1:
The patent applies different dielectric materials with different properties to different regions: low-k dielectric material is used in the first IMD layer for speed optimization, while a denser dielectric material is used in the second IMD layer for reliability enhancement. This local differentiation allows simultaneous optimization of both RC delay and TDDB reliability.
Solution Approach 2:
The patent employs a composite inter-metal dielectric structure consisting of two distinct IMD layers with different material compositions. The first IMD layer uses low-k dielectric material while the second IMD layer uses a denser dielectric material, creating a composite structure that combines the advantages of both materials for different functional requirements.
2Speed
If low-k or ultra-low-k dielectric materials are used to reduce RC delay, then signal transmission speed is improved, but the dielectric layer becomes more susceptible to breakdown under high voltage stress
Solution Approach 1:
Different regions of the inter-metal dielectric structure are assigned different material qualities: the first IMD layer prioritizes low dielectric constant for signal speed, while the second IMD layer prioritizes high density and breakdown strength for voltage stress resistance. This spatial differentiation of material properties resolves the contradiction between speed and strength.
Solution Approach 2:
The patent resolves the contradiction by adding a vertical dimension to the dielectric structure, creating multiple stacked IMD layers with different material properties. Instead of using a single uniform material, the solution transitions from a one-dimensional to a multi-dimensional structure where each layer serves a specific functional purpose.
Data Source
AI summary
An embedded high-voltage semiconductor device includes a substrate with a low-voltage device region and a high-voltage device region; an ILD layer located on the substrate; a first interconnection metal layer located on the ILD layer in the low-voltage device region a; a first IMD layer between the ILD layer and the first interconnection metal layer; a second interconnection metal layer located on the ILD layer in the high-voltage device region; and a second IMD layer between the ILD layer and the second interconnection metal layer. The second IMD layer is denser than the first IMD layer.