Embedded Inductor Coils in Semiconductor Packages
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Solution Overview
Problem
Conventional semiconductor chips face challenges in providing regulated voltage at high current levels due to limitations in resistance and geometry, leading to significant I2R losses and performance penalties when incorporating inductors within the chip or on the package substrate.
Innovation Solution
The integration of conductive pillars and inductor coils within a molding layer, sandwiched between redistribution layers, which allows for the creation of solenoid inductor coils that minimize I2R losses and do not occupy space on the package substrate, along with a high permeability core for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inductors are incorporated within the chip or on the package substrate, then voltage regulation can be provided, but I2R losses increase and performance deteriorates due to resistance and geometry limitations
Solution Approach 1:
The patent transitions the inductor from a planar substrate-based structure to a three-dimensional embedded structure within the molding layer. The inductor coil is formed using vertical conductive pillars extending through the molding layer, creating a solenoid geometry that utilizes the third dimension (depth) rather than relying solely on two-dimensional substrate routing. This dimensional change reduces the effective resistance by shortening current paths and improving geometry, thereby reducing I2R losses while maintaining voltage regulation functionality.
Solution Approach 2:
The patent employs composite material structures for the inductor, combining conductive pillars (metallic conductors) embedded in an insulating molding layer material. The molding layer itself is a composite structure containing the conductive pillars, allowing the inductor to be integrated within the package while maintaining electrical isolation and mechanical support. This composite approach enables low-resistance current paths through the pillars while the molding material provides structural integrity and electrical insulation, reducing overall I2R losses.
2Reliability
If inductors are incorporated within the chip or on the package substrate, then voltage regulation can be provided, but the device occupies valuable space on the package substrate
Solution Approach 1:
The patent embeds the inductor structure within the existing molding layer of the semiconductor package, nesting the inductor coil and conductive pillars inside the three-dimensional volume of the molding material. This nesting approach integrates the voltage regulation component within the already-present package structure rather than adding it as a separate external component, thereby utilizing unused space within the molding layer and avoiding occupation of additional package substrate area.
Solution Approach 2:
The patent moves the inductor from a two-dimensional substrate plane to a three-dimensional embedded structure within the molding layer. By forming vertical conductive pillars that extend through the molding layer and creating a solenoid coil geometry, the inductor utilizes the vertical dimension (depth) of the package structure. This eliminates the need for large planar substrate area that would be required for traditional substrate-mounted inductors, as the inductor functionality is achieved within the existing vertical profile of the package.
3Reliability
If conventional voltage regulators with inductors are used, then voltage regulation is achieved, but the electrical pathways become longer and inductance increases, reducing high speed performance
Solution Approach 1:
The patent merges the inductor structure with the existing package interconnect architecture by using the same conductive pillars and redistribution layer structures for both power delivery and inductor functionality. The conductive pillars that provide vertical interconnect between layers are simultaneously used to form the inductor coil, eliminating separate inductor interconnect paths. This merging reduces the total length of electrical pathways and minimizes additional inductance that would otherwise be introduced by separate inductor mounting and connection structures.
Solution Approach 2:
The patent creates vertical electrical pathways through the use of conductive pillars extending through the molding layer, transitioning from horizontal substrate-based routing to vertical three-dimensional interconnect. This dimensional change shortens the electrical pathway length by utilizing the vertical dimension directly above the active circuitry, rather than routing currents through extended horizontal paths on the substrate. The reduced pathway length and optimized geometry lower inductance, thereby improving high-speed performance while maintaining voltage regulation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient voltage regulation with reduced I2R losses and electromagnetic interference, allowing for high current applications without the limitations of existing technologies, while maintaining compactness and performance.
Implementation Method 1
some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil
Implementation Method 2
along with a high permeability core for enhanced performance
Data Source
AI summary
Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.