Embedded Off-Die Inductors for Low-Parasitic Chip Packaging
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Solution Overview
Problem
Conventional chip packaging schemes face challenges with reduced space for inductors due to increased IC density, leading to parasitic effects and diminished performance from surface-mounted inductors, which are susceptible to parasitic losses and require complex routings.
Innovation Solution
The integration of embedded off-die inductors in a redistribution layer and a substrate, such as a package substrate or interposer, where one inductor is disposed adjacent the IC die and another in the substrate, forming a series connection to enhance inductance and reduce parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional surface mounted inductors are used, then space requirements are mitigated, but routing distances increase and performance diminishes
Solution Approach 1:
The patent introduces an intermediary structure - the redistribution layer (RDL) - that serves as both a routing medium and an inductor substrate. The RDL is positioned between the IC die and package substrate, acting as a mediator that allows inductor placement close to the die while maintaining electrical connectivity through controlled routing paths within the RDL structure itself.
Solution Approach 2:
The patent transitions from surface-mounted inductors (2D placement on package substrate) to embedded inductors within the RDL (utilizing the vertical dimension between die and substrate). This dimensional shift allows inductors to be positioned in the Z-direction closer to the die, reducing routing distances while maintaining compact footprint.
2Quantity of substance
If IC device density increases, then area utilization improves, but parasitic effects increase
Solution Approach 1:
The patent extracts the inductor function from the traditional package substrate location and relocates it to the RDL layer adjacent to the IC die. This separation removes the inductor from the high-density routing environment of the package substrate, thereby reducing exposure to parasitic effects from surrounding circuits and power grids while maintaining compact device density.
Solution Approach 2:
The patent creates a localized low-parasitic environment by placing inductors in the RDL layer specifically positioned near the IC die, where the electromagnetic environment is more controlled and isolated from the complex routing of the package substrate. This local quality improvement reduces parasitic coupling while maintaining overall high device density.
3Power
If inductor area increases, then inductance improves, but valuable substrate core space is occupied
Solution Approach 1:
The patent utilizes the vertical dimension by embedding inductors within the RDL layer structure rather than placing them on the package substrate surface. This allows inductors to occupy space in the Z-direction (between die and substrate) rather than consuming valuable substrate core area, enabling larger inductor footprints without reducing available substrate real estate.
Solution Approach 2:
The patent nests the inductor structures within the RDL layer, which itself is nested between the IC die and package substrate. This nested arrangement allows inductors to be housed within the existing package structure without requiring additional substrate core space, effectively utilizing the vertical stacking volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased inductance and power efficiency, freeing up space within the IC die for additional components and improving signal path capacitance while reducing power consumption and assembly time.
Implementation Method 1
embedded off-die inductors coupled in series... one inductor embedded in a redistribution layer adjacent an integrated circuit die of the chip package and a second inductor embedded in a substrate of the chip package
Data Source
AI summary
A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.