Embedded InFO Adapter for 3D-IC Power Distribution

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Solution Overview

Problem

The semiconductor industry faces challenges in miniaturization and power distribution network performance due to limitations in current packaging techniques for stacked semiconductor devices, which hinder further reductions in physical size and improvements in integration density.

Innovation Solution

A three-dimensional integrated circuit (3D-IC) module socket system is developed, incorporating an embedded integrated fan-out (InFO) adapter with integrated passive and active devices, which is stacked between a socket and a system-on-wafer package, enhancing power distribution network performance and current handling by optimizing the layout and integration of semiconductor dies and vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If stacked semiconductor devices are used to reduce physical size, then integration density improves, but power distribution network performance deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidpower distribution network performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar power distribution to three-dimensional power distribution by stacking multiple semiconductor dies with embedded passive devices. The power distribution network is extended into the vertical dimension, allowing power and ground signals to be distributed through multiple layers via through-vias, thereby maintaining performance while achieving higher integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Passive devices such as capacitors and inductors are embedded within the semiconductor die structure itself, nested between active device layers. This nesting approach integrates power distribution functions directly into the stacked die architecture, eliminating the need for separate discrete components and maintaining compact form factor while improving power network performance.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The semiconductor device is divided into multiple separate dies that are stacked and bonded together. Each die can be fabricated using standard process nodes without requiring sub-20 nm manufacturing, thereby reducing manufacturing complexity. The segmentation into functional layers (active devices, passive devices, interconnect layers) allows each to be optimized independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Carrier substrates are used as intermediaries during the fabrication and bonding process. Multiple semiconductor dies are first formed on separate carrier substrates, then bonded together in a stacked configuration. The carrier substrates facilitate handling, alignment, and bonding processes, reducing the complexity of direct die-to-die integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If sophisticated bonding techniques are used to stack semiconductor devices, then integration density improves, but ease of manufacture deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidease of manufacture
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

Semiconductor dies are prepared in advance on separate carrier substrates with pre-formed contact pads, metallization layers, and embedded passive devices. The carrier substrates remain attached during the bonding process, providing mechanical support and simplifying alignment. This preliminary preparation eliminates the need for complex real-time alignment and bonding techniques.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Carrier substrates serve as intermediaries that simplify the bonding process. Instead of directly bonding fragile semiconductor dies to each other, the dies are first bonded to robust carrier substrates, which then serve as handles for manipulation and alignment during subsequent die-to-die bonding. This intermediary approach significantly eases the manufacturing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11121052B2Integrated fan-out device, 3D-IC system, and method
Publication Date: 2021.09.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11121052B2 patent drawing
  • US11121052B2 patent drawing
  • US11121052B2 patent drawing

AI summary

A three dimensional integrated circuit (3D-IC) module socket system includes an integrated Fan-Out (InFO) adapter having one or more integrated passive devices (IPDs) embedded in the InFO adapter. The InFO adapter is also integrated into the 3D-IC module socket system by stacking the InFO adapter between a socket and a SoW package. The InFO adapter with embedded IPDs allows for more planar area of the SoW package to be available for interfacing the socket and provides a short distance between the embedded IPDs and computing dies of the SoW package which enhances a power distribution network (PDN) performance and improves current handling of the 3D-IC module socket system.