Embedded Interconnect Capacitor Layout for Low-Impedance Chip Stacks
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Solution Overview
Problem
In semiconductor packaging, designing an interconnect structure that effectively manages impedance and noise across multiple frequency ranges is challenging, especially for high-performance chips, as traditional decoupling capacitors often occupy significant space and are not optimally positioned for efficient power delivery.
Innovation Solution
The integration of a decoupling capacitor within the interconnect package, referred to as an integrated stack capacitor (ISC), which is embedded in the redistribution layer close to the semiconductor chips, reduces impedance and noise by providing a high-capacitance density solution with a small footprint, potentially replacing die-side or land-side capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional die-side or land-side capacitors are used for decoupling, then sufficient capacitance can be provided, but the package footprint increases and the capacitor is not optimally positioned for efficient power delivery
Solution Approach 1:
The capacitor is merged with the interconnect package structure, specifically embedded within the redistribution layer. This integration allows the capacitor to serve dual purposes: providing decoupling functionality and acting as part of the interconnect architecture, thereby reducing the overall package footprint while maintaining optimal positioning near the semiconductor chip for efficient power delivery
Solution Approach 2:
The capacitor is positioned in the vertical dimension within the redistribution layer rather than being placed laterally on the package substrate. This vertical integration into the interconnect package allows the capacitor to be located close to the semiconductor chip in the Z-direction, achieving optimal power delivery performance without increasing the lateral footprint of the package
2Area of stationary object
If capacitor size is reduced to decrease footprint, then package area is minimized, but capacitance density may be insufficient for effective decoupling
Solution Approach 1:
The capacitor structure utilizes local quality enhancement by employing multiple dielectric layers with different properties and configuring the electrode arrangement to maximize capacitance density in the localized region where the capacitor is embedded in the redistribution layer, achieving high decoupling performance in a compact volume
3Ease of manufacture
If capacitor is positioned away from semiconductor chip, then manufacturing is easier, but impedance and noise in power delivery increase
Solution Approach 1:
The capacitor is positioned in the vertical dimension within the redistribution layer directly above or below the semiconductor chip connection points, rather than being placed laterally distant on the package substrate. This vertical integration minimizes the current path length and reduces parasitic inductance, thereby lowering impedance and noise while maintaining manufacturability through standard redistribution layer processing
Data Source
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AI summary
Provided is a semiconductor package which includes: a die stack including at least two semiconductor chips laterally arranged and isolated from each other by a molding material; and an interconnect package disposed above or below the die stack and connecting the semiconductor chips to each other, wherein the interconnect package having a smaller lateral width than the die stack is entirely overlapped by the die stack in a vertical direction, and a capacitor is disposed inside the interconnect package and connected to at least one of the semiconductor chips and configured to be connected to a voltage source and a ground.