Embedded Interconnect IC Packaging for Miniaturization
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Solution Overview
Problem
Conventional semiconductor package structures face challenges in miniaturization, reliability, and cost-effectiveness, particularly in portable devices, where they require smaller, thinner, and more densely packed components with improved performance and lower manufacturing costs.
Innovation Solution
An integrated circuit packaging system is developed with an adhesive attached to the integrated circuit, connected to a plated interconnect pad, and embedded interconnects, which are encapsulated with an epoxy molding compound, exposing the interconnects and adhesive from one side, allowing for secure attachment and reduced package height without a carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor package structures are used, then components can be packaged with basic protection, but the package size and thickness cannot be sufficiently reduced for portable devices
Solution Approach 1:
The patent transitions from conventional planar packaging to a three-dimensional stacked architecture where multiple integrated circuit dice are vertically arranged and interconnected through embedded interconnects. This vertical stacking approach dramatically reduces the horizontal footprint and overall package thickness while maintaining or increasing functional capacity, directly addressing the need for smaller packages in portable devices without compromising reliability through proper interconnect design and encapsulation.
Solution Approach 2:
The patent implements a nested structure where multiple integrated circuit dice are stacked within a single package envelope, with each die containing functional circuits and interconnect structures. The embedded interconnects are nested within the package substrate, and encapsulation material is nested around all components to provide protection. This nested arrangement maximizes space utilization and achieves miniaturization while maintaining structural integrity and reliability.
2Quantity of substance
If multiple integrated circuit dice are stacked or package-on-package approaches are used, then packaging density increases, but manufacturing cost increases and reliability challenges arise
Solution Approach 1:
The patent combines multiple functional elements into an integrated structure: multiple integrated circuit dice are combined within a single package, embedded interconnects are combined with the package substrate, and encapsulation is combined to protect all elements simultaneously. This merging approach achieves high packaging density while streamlining the manufacturing process by creating a unified structure that can be produced in fewer discrete steps compared to traditional multi-stage assembly methods.
Solution Approach 2:
The patent incorporates embedded interconnects into the package substrate before final assembly, and performs preliminary bonding of integrated circuit dice to the substrate with adhesive. These preliminary actions are performed in a controlled manner during the packaging process itself, allowing subsequent interconnect formation and encapsulation to proceed efficiently. This preliminary preparation reduces overall manufacturing complexity and cost while enabling high-density stacking.
3Length of stationary object
If package configurations are made smaller and thinner, then portability improves, but the structural integrity and protection of integrated circuits are compromised
Solution Approach 1:
The patent employs composite material structures where an encapsulation material (such as epoxy or polymer) is used to encapsulate and protect the integrated circuit dice and interconnects. This encapsulation layer provides mechanical strength, environmental protection, and structural integrity to the thin package structure. The combination of rigid interconnect elements, adhesive bonding layers, and protective encapsulation material creates a composite structure that maintains strength despite reduced overall package thickness.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the package: embedded interconnects provide localized electrical connectivity and structural support at critical bonding interfaces, adhesive layers provide localized bonding strength between dice and substrate, and encapsulation material provides distributed protection across the entire package. This localized optimization of material properties ensures structural integrity is maintained throughout the thin package without requiring uniform thickening of all components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a lower profile, increased connectivity, improved reliability, and reduced manufacturing costs by eliminating the need for a carrier, enhancing package rigidity and protecting the integrated circuit from damage.
Implementation Method 1
providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad
Implementation Method 2
forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad; attaching an embedded interconnect to the plated interconnect pad; and forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side and the plated interconnect pad and the adhesive exposed from the encapsulation second side.


