Embedded Interconnect Die Package Substrate for Low-Loss Routing
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Solution Overview
Problem
The existing Chip-on-Wafer-on-Substrate (CoWoS) packages have limitations such as large size, high insertion loss, and reliability issues due to embedded interconnect dies, which affect electrical routing and input/output ability, and result in significant warpage and reduced yield.
Innovation Solution
The interconnect die is embedded within a build-up package substrate rather than being embedded in CoWoS packages, allowing discrete package components to be directly bonded to the substrate, reducing warpage and improving yield by enabling more efficient electrical routing and reduced insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnect dies are embedded in CoWoS packages, then electrical interconnection is achieved, but package size increases and warpage increases
Solution Approach 1:
The patent extracts the interconnect die from the CoWoS package structure and places it directly on the package substrate. This separation allows the CoWoS package to be smaller while maintaining the electrical interconnection function through direct substrate mounting, thereby resolving the contradiction between achieving electrical interconnection and minimizing package size.
Solution Approach 2:
The patent changes the spatial arrangement by moving the interconnect die from an embedded position within the CoWoS package to a surface-mounted position on the package substrate. This dimensional repositioning reduces the vertical profile and overall package volume while preserving the electrical connection pathway.
2Reliability
If interconnect dies are embedded in CoWoS packages, then electrical routing is provided, but insertion loss increases
Solution Approach 1:
The patent extracts the interconnect die from the embedded position and places it directly on the package substrate, creating shorter and more direct signal paths. This eliminates the complex signal routing through multiple embedded layers and interfaces, reducing signal attenuation and insertion loss while maintaining the electrical routing function.
3Reliability
If interconnect dies are embedded in CoWoS packages, then electrical interconnection is achieved, but manufacturing yield decreases
Solution Approach 1:
By extracting the interconnect die from the complex embedded CoWoS structure and implementing direct substrate mounting, the patent simplifies the manufacturing process. This reduces the number of fabrication steps, alignment requirements, and potential defect sources, thereby improving manufacturing yield while achieving the same electrical interconnection function.
Data Source
AI summary
A method includes forming a build-up package substrate, which includes forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs, forming a first plurality of through-vias on the first plurality of RDLs, bonding an interconnect die to the second plurality of RDLs, encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant, and forming a third plurality of RDLs over the first encapsulant. The third plurality of RDLs are electrically connected to the first plurality of through-vias. An organic package substrate is bonded to the build-up package substrate. The build-up package substrate and the organic package substrate in combination form a compound organic package substrate. A first package component and a second package component are bonded to the compound organic package substrate, and are electrically interconnected through the interconnect die.