Embedded Local Interconnect Packaging Without Interposers
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and component density in semiconductor devices due to warpage mismatch and thermal expansion coefficient mismatch between integrated circuit packages and core substrates, necessitating the use of interposers that increase fabrication complexity.
Innovation Solution
A semiconductor package design that eliminates the need for interposers by using a solder-free connection between embedded local interconnect components and a redistribution structure, which provides increased communication bandwidth and reduces thermal expansion mismatch, while maintaining low contact resistance and high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers are used to connect integrated circuit packages to core substrates, then reliability is improved by addressing warpage mismatch and thermal expansion coefficient mismatch, but device complexity increases due to additional fabrication steps and structural components
Solution Approach 1:
The patent removes the interposer component from the package structure entirely. Instead of using an interposer to bridge the integrated circuit package and core substrate, the design directly couples these components through solder balls, eliminating the intermediate layer that causes fabrication complexity while maintaining connection reliability through direct bonding
Solution Approach 2:
The patent merges the functions previously performed by separate interposer and solder ball components into a direct coupling structure. The integrated circuit package is directly soldered to the core substrate, combining the connection functions into a single integrated assembly that reduces overall device complexity while maintaining reliability
2Quantity of substance
If minimum feature size is reduced to increase integration density, then component density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the packaging architecture from traditional lateral arrangements to a vertical stacked configuration with the integrated circuit package positioned above the core substrate. This parameter change in spatial arrangement allows higher integration density without proportionally increasing manufacturing precision requirements for lateral feature dimensions
3Area of stationary object
If Package-on-Package technology is used to achieve small footprints, then area is reduced, but warpage mismatch between packages increases
Solution Approach 1:
The patent applies local quality by using a core substrate with specific structural characteristics (such as recessed regions or non-planar features) that are tailored to match the integrated circuit package geometry. This localized structural adaptation reduces warpage mismatch in the critical bonding interface area while maintaining the compact footprint advantage of PoP architecture
Data Source
AI summary
In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.