Embedded Interconnect Die Packaging for Overlay Shift Reduction
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Solution Overview
Problem
The increasing size of interposers in Chip-on-wafer-on-substrate packages leads to narrower overlay windows, increasing the likelihood of cold joints and other manufacturing issues.
Innovation Solution
Embedding interconnect dies, such as local silicon interconnect (LSI) dies, within a package substrate, and forming through-vias directly from the substrate, which allows for smaller interposers and reduces overlay shift by distributing computing components more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If interposers are made increasingly larger to meet computing power requirements, then computing power is improved, but overlay window becomes narrower and cold joints become more likely
Solution Approach 1:
The patent divides the monolithic interposer into multiple smaller interposer segments or dies. Each segment has its own size that maintains an adequate overlay window, while collectively they provide the large area needed for high computing power. This segmentation allows parallel processing and maintains manufacturing precision while achieving the required computing capacity.
Solution Approach 2:
The patent transitions from a two-dimensional planar interposer to a three-dimensional stacked architecture where multiple interposer layers are vertically arranged. This vertical stacking enables the system to achieve large effective area and high computing power without requiring each individual interposer layer to be large, thus maintaining adequate overlay windows for manufacturing precision.
2Power
If interposers are made increasingly larger, then computing power is improved, but cold joints become more likely to occur
Solution Approach 1:
By segmenting the large interposer into smaller units, the patent reduces the absolute size of each bonding interface. Smaller bonding areas are less prone to cold joints and manufacturing defects. The segmented structure also allows for better stress distribution and thermal management, further improving reliability.
Solution Approach 2:
The patent incorporates preliminary underfill material application and encapsulation structures before final bonding. These preliminary actions prepare the bonding interfaces with appropriate stress relief and alignment features, reducing the likelihood of cold joints during the bonding process and improving overall joint reliability.
Data Source
AI summary
A method includes forming a composite package substrate, which includes forming through-openings in a dielectric core, filling the through-openings to form a first plurality of through-vias in the dielectric core, and forming a first interconnect structure and a second interconnect structure on opposing sides of the dielectric core. The first interconnect structure is connected to the second interconnect structure through the first plurality of through-vias. The method further includes bonding a local interconnect die to the first interconnect structure, forming a second plurality of through-vias directly from the first interconnect structure, encapsulating the second plurality of through-vias and the local interconnect die in an encapsulant, and forming a third interconnect structure over and electrically coupling to the local interconnect die and the second plurality of through-vias.