Embedded Interconnect Structures for Planar Low-Temperature Bonding
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Solution Overview
Problem
In the manufacturing of integrated circuits, conductive interconnect structures often experience dishing and erosion during the bonding process, leading to surface topography variance and unreliable bonds, which can result in voids and reduced reliability of metal-to-metal bonds.
Innovation Solution
The implementation of an embedded layer, such as a dielectric material or conductive material, is used to mitigate dishing and erosion by filling recesses and voids, creating a planar bonding surface and suppressing surface mobility of metal atoms, allowing for reliable direct bonding at lower temperatures with larger and mixed-sized conductive interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If direct bonding technique is used to bond stacked dies, then bonding process is simplified, but surface topography variance causes unreliable bonds and voids
Solution Approach 1:
The patent applies preliminary action by performing CMP planarization on the bonding surfaces of dies before stacking and bonding them together. This pre-treatment removes surface irregularities and creates flat bonding interfaces, preventing void formation and ensuring reliable bonds. The planarization step is executed in advance of the bonding process, allowing the subsequent bonding to proceed without the harmful effects of surface topography variance.
2Area of moving object
If conductive interconnect structures are made larger, then interconnection capability is improved, but dishing and erosion during bonding increase
Solution Approach 1:
The patent applies preliminary action by performing CMP planarization on the bonding surfaces before stacking and bonding the dies. This pre-treatment removes surface irregularities including dishing and erosion that occur on larger conductive interconnect structures, creating flat bonding interfaces that maintain both large interconnect area and high surface precision.
Solution Approach 2:
The patent applies parameter changes by modifying the surface topology parameter through CMP planarization, transforming the surface from irregular (with dishing and erosion) to flat. This parameter change allows larger interconnect structures to maintain their area advantage while eliminating the surface topography defects that would otherwise compromise bonding quality.
3Temperature
If bonding temperature is reduced, then thermal stress is minimized, but bonding reliability decreases
Solution Approach 1:
The patent applies preliminary action by performing CMP planarization to create flat bonding surfaces before bonding. This pre-treatment ensures that even at lower bonding temperatures, the intimate contact between planarized surfaces enables reliable metal-to-metal bonds, eliminating the need for high temperatures that would otherwise be required to compensate for surface irregularities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of direct bonding by reducing surface topography variance, preventing voids, and enabling the use of larger conductive interconnect structures, while maintaining low-temperature bonding capabilities, thus improving the consistency and efficiency of the bonding process.
Implementation Method 1
The implementation of an embedded layer, such as a dielectric material or conductive material, is used to mitigate dishing and erosion by filling recesses and voids
Implementation Method 2
suppressing surface mobility of metal atoms
Implementation Method 3
allowing for reliable direct bonding at lower temperatures with larger and mixed-sized conductive interconnect structures
Data Source
AI summary
Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.