Embedded Interconnection Layers for Solder Bridging Prevention
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Solution Overview
Problem
In the miniaturization of semiconductor elements, solder bridging and overspread issues between neighboring traces pose challenges, complicating the packaging process and requiring innovative solutions to enhance trace density and design flexibility.
Innovation Solution
A manufacturing method involving a substrate structure with a conductive structure comprising a first metal layer, a second metal layer with a larger surface area, and a third metal layer, where the third metal layer's surface area is greater than the second, forming a conductive structure embedded in a dielectric layer to prevent solder bridging and allow for increased trace density and flexible design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of semiconductor elements is reduced to increase I/O pins, then the number of I/O pins is increased, but solder bridging occurs between neighboring traces and the packaging process becomes complicated
Solution Approach 1:
The patent introduces a vertical dimension by forming multiple metal layers (first, second, and third metal layers) stacked at different heights. The third metal layer is positioned above the second metal layer, creating a three-dimensional conductive structure that increases I/O pin density without increasing planar trace density, thereby preventing solder bridging while maintaining reliability
Solution Approach 2:
The conductive structure is segmented into multiple discrete metal layers separated by dielectric layers. Each metal layer serves as an independent conductive plane, allowing traces to be routed at different heights and preventing solder bridging between adjacent traces by spatial separation in the vertical dimension
2Quantity of substance
If the circuit pitch and circuit width are reduced to increase I/O pins, then the number of I/O pins is increased, but the packaging process becomes complicated
Solution Approach 1:
By utilizing the vertical dimension with multiple stacked metal layers, the patent achieves higher I/O pin counts without reducing circuit pitch or width in the planar direction. This eliminates the need for complex fine-pitch packaging processes while maintaining design simplicity
Solution Approach 2:
The dielectric layers serve multiple functions: they provide electrical insulation between metal layers, act as a solder mask to prevent solder bridging, and provide mechanical support for the conductive structure. This multi-functionality simplifies the packaging process by eliminating the need for separate solder mask layers
3Reliability
If solder mask is used to prevent solder bridging, then solder bridging is prevented, but manufacturing cost increases
Solution Approach 1:
The dielectric layers are designed to perform both insulation and solder mask functions simultaneously. By forming the dielectric layer between metal layers with appropriate material properties, it prevents solder bridging without requiring an additional dedicated solder mask layer, thereby reducing manufacturing cost while maintaining reliability
Data Source
AI summary
A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.