Embedded Interposer Package Layout for Shorter Chip Connections
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high performance, high speed, and compact size due to limitations in integrating multiple semiconductor chips effectively.
Innovation Solution
A semiconductor package design incorporating a substrate with a core portion, buildup portions, and an interposer chip that includes a base layer and redistribution layer, along with vias for electrical connections, allowing for efficient chip-to-chip connections and improved thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on a substrate, then functional integration is improved, but electrical connection length increases
Solution Approach 1:
An interposer chip is introduced as an intermediary component between multiple semiconductor chips. The interposer chip includes a redistribution layer with conductive patterns that route electrical signals, and via holes that provide vertical connections. This mediator structure enables short-distance electrical connections between chips by redistributing signal paths through the interposer's conductive layers, thereby reducing overall electrical connection length while maintaining functional integration of multiple chips.
2Adaptability or versatility
If multiple semiconductor chips are mounted on a substrate, then device functionality is improved, but thermal radiation efficiency deteriorates
Solution Approach 1:
The interposer chip serves as a thermal management intermediary between the semiconductor chips and the substrate. It incorporates thermal vias filled with conductive material that extend vertically through the interposer structure, providing dedicated thermal conduction paths. These thermal vias transfer heat generated by multiple chips directly to the substrate's heat dissipation structures, improving thermal radiation efficiency while maintaining the functional integration of multiple devices.
3Productivity
If an interposer chip with redistribution layer is used, then electrical connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The interposer chip structure is segmented into distinct functional layers: a base layer providing mechanical support, a redistribution layer with conductive patterns for signal routing, and via holes for vertical connections. This segmentation allows each layer to be optimized and manufactured separately using standard semiconductor fabrication processes, then assembled together. The modular segmented structure reduces manufacturing complexity compared to attempting to create all connections in a single monolithic structure.
4Reliability
If via holes are formed to penetrate the base layer, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Via holes are formed and filled with conductive material during the interposer chip manufacturing process before the interposer is mounted to the substrate. This preliminary formation of via structures ensures precise alignment and electrical connectivity are established in advance. The via holes are created using photolithography and etching processes with predefined patterns, and conductive material is deposited and filled beforehand, eliminating the need for high-precision alignment during final assembly and reducing manufacturing precision requirements at the mounting stage.
Data Source
AI summary
A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.