Embedded Interposer Package Substrate for High-Density Routing
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Solution Overview
Problem
Conventional package substrates fail to meet the increasing demands for high wiring density and performance in semiconductor chips, necessitating a more advanced packaging solution.
Innovation Solution
A package substrate with an embedded interposer and insulating protective layer, featuring conductive vias and pads, is developed to reduce the electrical connection path between active and passive components, enhancing stability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional package substrates are used, then the structure is simple and easy to manufacture, but the wiring density and electrical performance cannot meet the demands for high-speed and high-performance semiconductor chips
Solution Approach 1:
The patent transitions from conventional 2D planar packaging to 3D vertical packaging by embedding the interposer within a recess of the substrate. This dimensional change enables multiple wiring layers and stacked component arrangements, achieving high wiring density and supporting nano-scale circuits while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The interposer is nested within a recess defined by the substrate, with the insulating protective layer encapsulating the interposer. This nested structure integrates multiple functional elements (substrate, interposer, protective layer) into a compact 3D configuration, increasing wiring density without proportionally increasing overall package complexity
2Reliability
If the electrical connection path is lengthened in conventional packages, then manufacturing is easier, but voltage stability and electrical performance deteriorate
Solution Approach 1:
The interposer acts as an intermediary component between the substrate and overlying components. It provides a dedicated electrical connection path through conductive vias that directly connect substrate pads to upper-layer conductors, reducing connection length and improving voltage stability without requiring complex external routing
Solution Approach 2:
The patent uses vertical conductive vias through the interposer to create three-dimensional electrical connections. This vertical routing through the z-dimension significantly shortens the electrical connection path compared to traditional planar routing, enhancing voltage stability and electrical performance
3Productivity
If high wiring density is achieved through conventional means, then more circuits can be accommodated, but the manufacturing process becomes overly complex and incompatible with existing IC infrastructure
Solution Approach 1:
The interposer serves multiple functions simultaneously: it provides electrical connections through conductive vias, offers mechanical support within the recess, enables wiring redistribution, and provides a platform for mounting additional components. This multi-functionality achieves high wiring density while using standard manufacturing techniques applicable to existing IC infrastructure
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific regions: the interposer region contains conductive vias for electrical connections, the recess provides mechanical containment, and the insulating protective layer provides localized insulation. This localized differentiation achieves high wiring density in critical areas without requiring complex changes throughout the entire manufacturing process
Data Source
AI summary
A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.