Method of fabricating a semiconductor package

The patent introduces an interposer chip as an intermediary component between the substrate and semiconductor chips. This interposer chip includes a redistribution layer with high line density that acts as a mediator to achieve flexible wiring connections. The redistribution layer with patterns having different widths allows for optimized signal routing, while the interposer chip itself serves as the intermediate structure that manages the complexity of connecting multiple chips with varying pin configurations.

The patent transitions from horizontal/w lateral routing to vertical routing by implementing vias that extend in the thickness direction of the interposer chip. This dimensional change allows electrical connections to be made more directly between upper and lower surfaces, reducing the overall connection length. The vertical via structure provides a more direct pathway for electrical signals compared to traditional planar routing methods.

The patent employs composite material structures in the interposer chip, combining conductive materials for the high line density redistribution layer with thermally conductive materials for heat dissipation. The redistribution layer uses high-conductivity metal patterns for electrical performance, while the substrate and surrounding structures incorporate materials with high thermal conductivity to facilitate heat removal from the densely packed wiring regions.

The patent implements preliminary actions by pre-fabricating the interposer chip with its redistribution layer and via structures before embedding it into the substrate's core portion. This allows the complex interposer structure to be manufactured separately using optimized semiconductor fabrication processes, then integrated into the final package. The embedding process itself is performed as a distinct step after the interposer is prepared, separating the complex fabrication tasks into manageable stages.