Embedded Interposer Substrate for Thermal Stress Reduction
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Solution Overview
Problem
Conventional packaging substrates face issues with thermal stress and compatibility with high-density nano-scale semiconductor chips due to mismatched thermal expansion coefficients and inadequate pitch density, leading to reduced reliability and fabrication challenges.
Innovation Solution
A packaging substrate with an embedded interposer and a redistribution layer is developed, featuring conductive pads and metal posts or bumps to match the thermal expansion coefficient of the semiconductor chip, reducing thermal stress and enhancing heat dissipation, while allowing for high-density circuit compatibility without altering existing IC industry supply chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional packaging substrate with micro-scale pitch bonding pads is used, then the substrate structure is simple and easy to manufacture, but it is not suitable for high-density nano-scale circuits with reduced pitches
Solution Approach 1:
The invention divides the packaging substrate into two functional layers: a carrier substrate providing mechanical support and a separate interposer layer providing the fine-pitch bonding interface. This segmentation allows each layer to be optimized independently - the carrier for structural integrity and the interposer for high-density circuit compatibility.
Solution Approach 2:
The interposer acts as an intermediary component between the coarse-pitch carrier substrate and the fine-pitch semiconductor chip. It translates the electrical connections from the carrier's micro-scale pads to the chip's nano-scale pads, enabling compatibility between different pitch scales without requiring the entire substrate to have ultra-fine pitch throughout.
2Reliability
If a packaging substrate with large CTE difference relative to the semiconductor chip is used, then material selection is easier and manufacturing is simpler, but thermal stress causes solder bumps to crack and reduces reliability
Solution Approach 1:
The invention applies local quality by making the interposer's material properties (specifically CTE) match the semiconductor chip's requirements locally at the bonding interface, while the carrier substrate can have different material properties optimized for its structural role. This localized material optimization protects the solder bumps from thermal stress without constraining the overall substrate material choices.
3Volume of moving object
If the packaging substrate thickness is reduced to improve miniaturization, then the overall device size is reduced, but heat dissipation capability is compromised
Solution Approach 1:
The invention addresses heat dissipation by transitioning from a purely planar heat spread approach to a three-dimensional solution with heat dissipation structures extending vertically from the carrier substrate. This allows the substrate to remain thin in the primary plane while providing thermal management pathways in the vertical dimension through embedded metal layers and protruding heat dissipation features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves product reliability by minimizing thermal stress and enabling the use of high-density nano-scale circuits, while reducing the overall substrate thickness and enhancing heat dissipation, thus addressing the limitations of conventional substrates.
Implementation Method 1
The embedded interposer has substantially the same coefficient of thermal expansion as the semiconductor chip... since the CTEs of the interposer and the semiconductor chip are close to each other, the present invention prevents large thermal stresses from occurring between the semiconductor chip and the interposer
Implementation Method 2
by embedding a metal post, a metal bump or a metal plate in the packaging substrate, the present invention facilitates dissipation of heat generated by the packaging substrate and the semiconductor chip
Data Source
Figure 1
Figure 2A~2E
Figure 2F~2J
AI summary
A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is disposed in the top surface and a plurality of first conductive terminals are disposed on the bottom of the recess. Further, a plurality of second conductive terminals are disposed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is disposed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is disposed on the other end of the conductive through via exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.