Embedded Interposer Chip Stack for High-Density Tier Interconnects
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Solution Overview
Problem
Current multi-tier chip packages with bridge dies have limited interconnection density due to partial overlap, restricting the number and density of interconnections between adjacent IC dies.
Innovation Solution
A chip complex with a passive interposer that covers the entirety of IC dies in both tiers, utilizing hybrid bonding and BEOL processes to increase interconnect density, and wafer-on-wafer bonding techniques for improved registration and reduced pitch between bond pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a bridge die is used to provide interconnection between adjacent IC dies, then interconnection between tiers is enabled, but the interconnect density is limited due to partial overlap of the bridge die with adjacent IC dies
Solution Approach 1:
The patent transitions from 2.5D partial overlap interconnection to full 3D stacking with complete overlap. The interposer is positioned directly between adjacent IC dies in the vertical dimension, enabling complete overlap and maximum interconnect density. This dimensional change eliminates the beachhead limitation and allows interconnections throughout the entire interface area.
Solution Approach 2:
The patent introduces a passive interposer as an intermediary component between IC dies in different tiers. This interposer provides through-silicon vias (TSVs) that enable vertical interconnections, acting as a mediator that facilitates high-density signaling between tiers without the limitations of bridge die partial overlap structures.
2Productivity
If conventional 2.5D chip modules are used, then interconnection is achieved, but manufacturing cost increases and manufacturing time extends
Solution Approach 1:
The patent segments the interconnection function into a dedicated passive interposer component with TSVs, separating it from the active IC dies. This segmentation allows parallel processing and assembly, reducing manufacturing time compared to conventional 2.5D chip modules that require complex sequential alignment and bonding steps.
Solution Approach 2:
The patent changes the structural parameters of the interconnection system by using complete overlap geometry and passive interposer materials. These parameter changes simplify the manufacturing process, enabling faster assembly and reduced costs compared to the complex 2.5D chip module structure.
3Use of energy by moving object
If bridge die is used with limited beachhead, then device complexity is reduced, but power consumption increases due to lower interconnect density
Solution Approach 1:
The patent uses full 3D vertical stacking with complete overlap to maximize interconnect density, enabling shorter signal paths and lower resistance. This dimensional optimization reduces power consumption compared to the limited 2.5D bridge die approach, as more interconnections can be packed into the same footprint area.
Solution Approach 2:
The patent replicates the interconnection pattern across the entire interposer surface through the passive structure with TSVs. This copying approach enables uniform high-density interconnections throughout the device, improving power efficiency by providing consistent low-resistance pathways for signal transmission between all tiers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances interconnect density and bandwidth between IC dies, reducing power consumption and manufacturing time, while eliminating the need for costly 2.5D chip modules and complex process steps, thereby improving compute performance and energy efficiency.
Implementation Method 1
The plurality of IC dies present in the first common tier are hybrid bonded to a bottom side of the passive interposer. The plurality of IC dies present in the second common tier are hybrid bonded to a top side of the passive interposer.
Implementation Method 2
wafer-on-wafer bonding techniques for improved registration and reduced pitch between bond pads
Data Source
AI summary
A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.