Embedded System Interruption Handling via Hardware Control Unit
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Solution Overview
Problem
Conventional embedded systems face inefficiencies in handling multiple interruption requests due to software-based priority control methods, which consume processor resources and can lead to system deadlocks when many requests are simultaneously asserted, causing lower priority service routines to be indefinitely delayed.
Innovation Solution
A hardware-based control unit with a scheduler and spare vector table is introduced to buffer and prioritize interruption requests, dynamically providing branch instructions to the processor for efficient execution of service routines, bypassing software-based priority control programs and enabling flexible priority configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based priority control programs are used to scan status registers and determine service routines, then the system can handle multiple interruption requests with priority ordering, but processor resources are consumed and system deadlocks may occur when many requests are simultaneously asserted
Solution Approach 1:
The patent replaces the software-based priority control mechanism with a hardware-based control unit that automatically manages interruption requests. The control unit includes a priority encoder that hardware-encodes priority levels and a buffer that hardware-manages service routine execution, eliminating the need for processor-executed scanning software and preventing deadlocks through dedicated hardware logic.
Solution Approach 2:
The patent introduces a control unit as an intermediary between the status registers and the processor. This control unit buffers interruption requests and automatically determines service routine execution based on priority encoding, acting as a mediator that prevents the processor from being directly involved in the complex scanning and priority determination process that could lead to deadlocks.
2Ease of operation
If the processor executes priority control programs to scan status registers sequentially, then service routines can be triggered in priority order, but lower priority service routines may be indefinitely delayed causing system deadlocks
Solution Approach 1:
The patent implements preliminary action by having the control unit pre-encode priority levels in hardware and pre-buffer interruption requests before the processor needs to handle them. The priority encoder continuously encodes priority levels based on asserted interruption requests, so when the processor executes service routines, the priority ordering is already established and ready, preventing indefinite delays.
Solution Approach 2:
The patent introduces dynamics by making the control unit's buffer and priority encoding adaptive to the current interruption state. The control unit dynamically updates priority encodings and buffer contents based on which interruption requests are currently asserted, allowing the system to flexibly respond to changing priority conditions without processor intervention.
3Productivity
If multiple interruption requests are simultaneously asserted with different priorities, then the system must determine execution order, but software-based scanning consumes processor resources and reduces system performance
Solution Approach 1:
The patent segments the interruption handling function into separate dedicated hardware components: a status register section, a control unit section with priority encoder and buffer, and a processor section. This segmentation allows the control unit to independently handle priority determination and service routine selection without consuming processor resources, while the processor focuses on executing service routines.
Solution Approach 2:
The control unit performs self-service by automatically encoding priorities and selecting service routines without processor involvement. The priority encoder continuously monitors status registers and automatically updates the buffer with the correct service routine addresses based on priority, making the control unit self-sufficient and freeing processor resources.
Data Source
AI summary
An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request. A processor receives an enable signal to initialize one of the service routines through a branch instruction. A control unit buffers the interruption requests to schedule executions of corresponding service routines. When a specific service routine is to be executed, the control unit provides the branch instruction pointing to entry address of the specific service routine and asserts the enable signal to the processor, such that the processor executes the branch instruction to initialize the specific service routine.