Embedded ISP in PCB Image Sensor Package
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Solution Overview
Problem
Current image sensor semiconductor packages face challenges with increased camera module size and signal integrity issues due to the separate location of the image signal processor (ISP) and the complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die, which requires long traces and affects high-speed data transfer.
Innovation Solution
The implementation of an image sensor semiconductor package that embeds an ISP within a printed circuit board (PCB) or uses an interposer with electrical vias to couple the CIS die directly with the PCB, eliminating the need for long traces and allowing for a more compact design with improved signal integrity through redistribution layers (RDLs) and efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the ISP is located separately from the CIS die, then the package structure is simpler, but the signal integrity deteriorates due to long traces affecting high-speed data transfer
Solution Approach 1:
The patent embeds the ISP within the PCB structure, merging the signal processing function into the substrate itself. This eliminates the need for separate ISP packaging and long external traces, thereby maintaining signal integrity while keeping the overall package structure manageable through integration.
Solution Approach 2:
The patent introduces an interposer with electrical vias as an intermediary component between the CIS die and the PCB. This interposer provides direct electrical coupling pathways that bypass the need for long traces on the PCB, thereby maintaining high-speed data transfer integrity while enabling flexible package design.
2Ease of manufacture
If long traces are used to connect ISP and CIS die, then the device can be assembled with separate components, but the data transfer speed decreases due to signal integrity issues
Solution Approach 1:
The interposer with electrical vias serves as a mediator that provides direct, short electrical pathways between the CIS die and ISP. This intermediary structure enables high-speed data transfer by eliminating long traces, while still allowing separate component assembly and placement on the PCB.
Solution Approach 2:
The patent transitions the electrical connection from a planar trace path on the PCB surface to a three-dimensional structure using vertical electrical vias through the interposer. This dimensional change creates direct vertical pathways that are much shorter than horizontal traces, thereby enabling high-speed data transfer while maintaining ease of assembly.
3Adaptability or versatility
If the package thickness is increased to accommodate separate ISP and CIS die, then each component can be optimized independently, but the overall device size increases
Solution Approach 1:
The patent embeds the ISP within the PCB structure, nesting the signal processing component inside the substrate rather than placing it externally. This nesting approach allows the ISP to be optimized independently through separate fabrication processes while maintaining a compact overall package thickness, as the ISP occupies space within the existing PCB volume.
Data Source
AI summary
An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.