Embedded IVR Package Structure for Shorter Signal Paths
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Solution Overview
Problem
Current electronic packaging solutions struggle to achieve miniaturization and high electrical performance while maintaining low power consumption and compactness, as integrating an integrated voltage regulator (IVR) directly onto a circuit board or package substrate increases manufacturing costs and requires redesigning of semiconductor chips, leading to inefficiencies in signal transmission and increased volume.
Innovation Solution
The proposed solution involves an electronic package structure with conductive vias and conductors on opposite sides of an electronic body, encapsulated in an insulating layer, allowing for the integration of an IVR within an encapsulating layer that reduces the need for redesigning packages and minimizes the size of electronic components, enabling closer integration with other components and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the IVR is integrated directly onto the circuit board, then the manufacturing cost is reduced, but the signal transmission distance becomes too long resulting in degraded electrical performance and increased power consumption
Solution Approach 1:
The patent transitions from planar integration (IVR on circuit board) to three-dimensional integration by placing the IVR on a separate semiconductor chip that is vertically stacked above the package substrate. This dimensional change enables both cost-effectiveness and short signal paths by bringing the IVR physically close to the processor chips while maintaining manufacturing simplicity through standard packaging processes.
Solution Approach 2:
The patent implements nested integration where the IVR chip is positioned within the package structure, specifically above the package substrate and in close proximity to the processor chips. This nesting arrangement allows the IVR to be integrated into the existing package hierarchy without requiring redesign of the semiconductor chips themselves, thus reducing manufacturing costs while achieving short signal transmission distances.
2Reliability
If the IVR is integrated onto the package substrate, then the signal transmission distance is shortened improving electrical performance, but the surface area and volume of the circuit board increases
Solution Approach 1:
The patent moves the IVR from the two-dimensional plane of the package substrate to a three-dimensional position above it, utilizing vertical space rather than horizontal surface area. This dimensional transition allows the IVR to be integrated without increasing the footprint or volume of the circuit board, while still achieving short signal transmission paths for improved electrical performance.
Solution Approach 2:
The patent employs a thin encapsulant layer to encapsulate the IVR chip and its connections, creating a compact structure that minimizes the volume occupied by the integrated components. This thin-film encapsulation approach allows for close integration of the IVR with the processor chips without significantly increasing the overall package volume.
3Adaptability or versatility
If multiple IVRs and semiconductor chips are attached on the package substrate, then more functions are achieved, but there is not enough room to accommodate additional components
Solution Approach 1:
The patent utilizes the vertical dimension above the package substrate to mount multiple IVRs and semiconductor chips in a stacked configuration. This three-dimensional arrangement enables increased functional capacity by accommodating more components without expanding the horizontal area of the package substrate, thus resolving the space constraint while maintaining versatility.
Solution Approach 2:
The patent implements a nested stacking architecture where multiple semiconductor chips and IVRs are vertically integrated above the package substrate. This nesting approach allows multiple functional components to be closely packed in the vertical direction, enabling high functional density without increasing the footprint of the package substrate.
4Adaptability or versatility
If the semiconductor chip size is expanded to integrate the IVR, then the IVR integration is achieved, but the miniaturization demand cannot be met
Solution Approach 1:
The patent segments the IVR function from the processor chip, implementing it as a separate integrated circuit chip. This segmentation allows the processor chip to maintain its original compact size while the IVR is integrated as a distinct component in the package structure, thus achieving integration capability without increasing the semiconductor chip volume.
Solution Approach 2:
The patent integrates the IVR chip within the package structure in close proximity to the processor chip, creating a nested arrangement where the IVR functions are embedded in the overall package rather than being part of the processor chip itself. This approach enables integration while maintaining miniaturization of the individual semiconductor chip.
Data Source
AI summary
An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.