Embedded JFETs Reduce Surface Electric Fields
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Solution Overview
Problem
Existing high-voltage Junction Field-Effect Transistors (JFETs) face challenges in efficiently managing high drain voltages and current flows due to high surface electric fields, which affect their pinch-off voltage and on-current performance.
Innovation Solution
The design incorporates a High-Voltage N-Well (HVNW) and P-Wells with P-type Buried Layers, forming a 3D current channel and adjusting the spacing between P-Wells to control pinch-off voltage, enabling efficient current flow and low turn-on resistance by using a combination of n-type and p-type doped regions and insulation regions to reduce surface electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing high-voltage JFET structures are used, then high drain voltages can be handled, but surface electric fields cause high pinch-off voltage and reduced on-current performance
Solution Approach 1:
The patent transitions from planar 2D JFET structures to 3D embedded JFET structures where the channel extends vertically through multiple wells and buried layers. This dimensional change allows the channel to be embedded within the substrate rather than being exposed at the surface, thereby reducing the harmful surface electric field effects while maintaining high-voltage handling capability.
Solution Approach 2:
The patent introduces intermediary structures including P-type buried layers, N-type wells, and P-type wells that act as mediators to control and redistribute electric fields. These intermediary doped regions create depletion zones that shield the channel from surface electric fields, reducing their harmful effects on pinch-off voltage and on-current performance.
2Ease of manufacture
If JFET channel is exposed at surface, then manufacturing is simpler, but surface electric fields increase pinch-off voltage and reduce on-current
Solution Approach 1:
The JFET channel is moved from a surface-exposed planar configuration to a 3D embedded configuration extending vertically through the substrate. The channel now resides within N-type wells and P-type wells rather than being exposed at the surface, reducing surface electric field effects while maintaining manufacturability through standard semiconductor processing techniques.
Solution Approach 2:
The JFET channel is nested within multiple concentric doped regions including N-type wells, P-type wells, and P-type buried layers. This nested structure allows the channel to be embedded deep within the substrate, shielded from surface effects, while still being accessible through standard top-down fabrication processes.
3Area of stationary object
If chip area is reduced by integrating JFETs with MOS transistors, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent designs the embedded JFET structure to share common substrates, wells, and processing steps with MOS transistors. The N-type wells and P-type wells serve dual purposes for both JFET and MOS device formation, allowing simultaneous fabrication of both device types on the same chip with reduced manufacturing precision requirements.
Solution Approach 2:
The patent optimizes doping concentrations, well depths, and spacing parameters to accommodate both JFET and MOS transistor requirements. By carefully controlling these parameters, the structure achieves compatible electrical characteristics for both device types while maintaining relaxed alignment tolerances during manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-voltage JFETs with adjustable pinch-off voltage and enhanced on-current performance, effectively managing high drain voltages and current flows, and reducing chip area by integrating with Metal-Oxide-Semiconductor transistors.
Implementation Method 1
By applying a bias voltage to a gate, the channel of the JFET may be pinched, so that the electric current flowing between the source and the drain is impeded or switched off
Implementation Method 2
using a combination of n-type and p-type doped regions and insulation regions to reduce surface electric fields
Data Source
AI summary
A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.