Embedded Laser Silicon Photonic Chip for Lower Optical Loss

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Solution Overview

Problem

Existing silicon photonic chips require remote lasers, leading to optical losses, increased fiber area, and larger optical engine sizes due to the need for optical fibers to couple light from the lasers to the chip.

Innovation Solution

A silicon photonic chip with an embedded laser, where the laser is disposed between the chip's surfaces and electrically connected via through-dielectric vias, allowing for direct light emission and reception within the chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If lasers are positioned remotely from the silicon photonics chip, then the laser can be separately manufactured and tested, but optical losses increase and the optical engine size increases due to required optical fiber coupling

Engineering Contradiction:
Improvelaser manufacturing and testingVSAvoidoptical losses
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent merges the laser with the silicon photonics chip by embedding the laser directly into the chip substrate. The laser is positioned within the chip package and electrically connected through through-dielectric vias, eliminating the need for separate laser mounting and optical fiber coupling. This integration reduces optical losses while maintaining manufacturing feasibility through co-fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces through-dielectric vias as intermediary structures that enable direct electrical connection between the embedded laser and external circuitry. These vias penetrate the dielectric layers of the chip, allowing current to reach the laser without requiring external wire bonds or complex interconnection structures, thus reducing both optical and electrical path lengths.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If lasers are positioned remotely from the silicon photonics chip, then the laser can be separately manufactured and tested, but the fiber area and overall optical engine size increase

Engineering Contradiction:
Improvelaser manufacturingVSAvoidoptical engine size
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The laser is merged with the silicon photonics chip into a single integrated package. The laser substrate is bonded to the chip substrate, and the laser is positioned within the chip package boundaries. This integration eliminates the need for separate laser mounting space and optical fiber routing space, significantly reducing the overall optical engine footprint.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a planar arrangement where the laser is mounted on the chip surface to a three-dimensional embedded configuration. The laser is positioned within the chip package volume and electrically connected through vertical through-dielectric vias. This dimensional change allows more efficient space utilization and reduces the horizontal footprint of the optical engine.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of energy

If lasers are embedded within the silicon photonic chip, then optical losses are reduced and the optical engine size is minimized, but the device complexity increases due to through-dielectric via fabrication

Engineering Contradiction:
Improveoptical lossesVSAvoidthrough-dielectric via fabrication
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The through-dielectric vias serve multiple functions: they provide electrical connection to the embedded laser, act as mechanical support structures, and enable thermal management pathways. This multi-functionality reduces the need for additional separate structures, offsetting the complexity of via fabrication with functional consolidation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent optimizes the dimensions, materials, and fabrication parameters of the through-dielectric vias to balance complexity with performance. By carefully controlling via diameter, depth, and filling material properties, the design achieves reliable electrical connection while minimizing the impact on optical performance and overall device complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces optical losses, minimizes the need for optical fibers, and results in a more compact optical engine size, enhancing the efficiency and size reduction of silicon photonic chips.

Implementation Method 1

the active region is configured to generate light

Methodology Applied
Scientific EffectLight emission from active region: Electroluminescence

Implementation Method 2

the silicon waveguide layer is configured to receive and guide light emitted by the laser

Methodology Applied
Scientific EffectLight guidance: Waveguide (optics)

Data Source

PatentUS20250202188A1Silicon photonic chip with embedded laser
Publication Date: 2025.06.19 NVIDIA CORP
  • US20250202188A1 patent drawing
  • US20250202188A1 patent drawing
  • US20250202188A1 patent drawing

AI summary

Silicon photonic chips with embedded lasers and methods for manufacturing silicon photonic chips with embedded lasers are described herein. Some embodiments of the present invention may be directed to a silicon photonic chip including a laser disposed in the silicon photonic chip between a first and second surface of the silicon photonic chip. The laser may include an anode and a cathode each extending substantially parallel to at least one of the first or second surface through at least a portion of the silicon photonic chip. The silicon photonic chip may include a first through-dielectric via electrically connecting the anode to the second surface of the silicon photonic chip and a second through-dielectric via electrically connecting the cathode to the second surface of the silicon photonic chip.