Embedded Conductive Lines in Fin Structures for Lower SRAM IR Drop
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Solution Overview
Problem
As semiconductor devices are scaled down, the increased resistance in smaller metallization lines can impair device performance, particularly in SRAM cells, leading to voltage drops and potential failure in operations like writing, due to higher IR drops and increased Vccmin requirements.
Innovation Solution
The method involves forming embedded metallization lines between active regions and gate structures, using a stack of channel and sacrificial layers, and depositing conductive lines between fin structures to reduce resistance and enhance performance, applicable to GAA transistors and FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If interconnect lines are scaled down to maintain device scaling, then device density and integration are improved, but resistance increases leading to higher IR drops and voltage drops
Solution Approach 1:
The patent transitions from planar 2D interconnect routing to 3D vertical routing through trench structures. Conductive lines are embedded in trenches that extend vertically between fin structures, allowing interconnects to route in the vertical dimension rather than only laterally. This dimensional change enables shorter, lower-resistance paths while maintaining compact device footprints, directly resolving the contradiction between device density and voltage stability.
Solution Approach 2:
The patent implements nested interconnect structures where conductive lines are embedded within trench structures that are themselves surrounded by dielectric materials and positioned between fin structures. This nested arrangement allows multiple interconnect layers to be vertically stacked and integrated within the three-dimensional device architecture, achieving high density without compromising electrical performance.
2Ease of manufacture
If conventional planar interconnect methods are used, then manufacturing simplicity is maintained, but resistance increases and device performance deteriorates
Solution Approach 1:
The patent segments the interconnect formation process into distinct stages: trench definition, trench filling with conductive material, and planarization. This segmentation allows each step to be optimized independently using existing manufacturing techniques, maintaining ease of manufacture while achieving the performance benefits of 3D embedded interconnects.
Solution Approach 2:
The patent performs preliminary actions by forming trenches and filling them with conductive material before final device assembly and testing. This preliminary structuring of interconnects ensures low-resistance paths are established early in the manufacturing process, preventing performance deterioration before devices are fully assembled.
Data Source
AI summary
Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.