Embedded Silicon-Less Link Chiplet Interposer for Dense Inter-Die Routing

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Solution Overview

Problem

Current semiconductor packaging technologies face limitations with silicon interposers due to high cost and performance issues, glass interposers due to manufacturing challenges and thermal conductivity, and organic interposers due to mechanical properties and lower I/O density.

Innovation Solution

A semiconductor packaging device featuring a high-density silicon-less link chiplet embedded in a lower-density redistribution layer interposer, which provides high inter-die connection density and routing density beyond high-bandwidth memory needs, using multilevel structures with interconnect dielectric material layers and electrically conductive structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If silicon interposers are used, then versatility and adaptability are improved, but cost increases and performance limitations occur

Engineering Contradiction:
ImproveversatilityVSAvoidcost
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The invention divides the interposer system into two distinct components: a silicon-less link chiplet providing high-density interconnect and a redistribution layer interposer providing routing functionality. This segmentation allows each component to be optimized independently, eliminating the need for expensive silicon interposers while maintaining versatility through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention merges the functions of high-density interconnect (previously requiring silicon) with redistribution layer routing into a single integrated package. The silicon-less link chiplet is embedded within the redistribution layer interposer, combining advantages of both approaches while eliminating silicon's disadvantages.

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If glass interposers are used, then cost is reduced, but manufacturing precision deteriorates due to surface defects and cracking

Engineering Contradiction:
ImprovecostVSAvoidsurface quality
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The invention extracts the high-density interconnect function from the glass interposer and places it in a separate silicon-less link chiplet. This removes the requirement for high manufacturing precision in the glass interposer, as the critical interconnect structures are now in the chiplet which can be manufactured with standard precision.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If glass interposers are used, then cost is reduced, but thermal conductivity deteriorates

Engineering Contradiction:
ImprovecostVSAvoidthermal conductivity
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The invention creates a composite structure where the silicon-less link chiplet (with superior thermal conductivity) is embedded in the glass redistribution layer interposer. This composite design allows the chiplet to provide thermal management for high-density interconnect while the glass provides cost-effective routing, achieving both low cost and good thermal conductivity.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS12199025B2Interposer structure containing embedded silicon-less link chiplet
Publication Date: 2025.01.14 CHENGDU ESWIN SYST IC CO LTD
  • US12199025B2 patent drawing
  • US12199025B2 patent drawing
  • US12199025B2 patent drawing

AI summary

An interposer structure is provided that can be used in semiconductor packaging to electrically connect a printed circuit board to a plurality of die. The interposer structure contains a high-density silicon-less link chiplet that is laterally surrounded by, and embedded in, a lower-density redistribution layer interposer.