Embedded Localized Capacitive Element for Circuit Board Noise Suppression
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Solution Overview
Problem
Circuit board designers face challenges in providing sufficient capacitance to high power, high switching speed integrated circuit devices without using surface-mounted capacitors, which are undesirable due to space constraints and increased inductance and resistance issues.
Innovation Solution
A localized, non-discrete, and distributive capacitive element is embedded within the circuit board, utilizing a dielectric layer between conductive layers to provide device-specific capacitance without occupying surface space, formed by a conductive element, an isolation gap, a dielectric element, and a resistive third conductive element, which reduces noise and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If surface mounted capacitors are used to provide device-specific capacitance, then sufficient capacitance for high power devices is achieved, but space on the circuit board surface is consumed and inductance and resistance increase
Solution Approach 1:
The patent transitions from surface-mounted capacitors (2D placement) to embedded capacitors formed within internal circuit board layers (3D integration). The capacitive structure is created between internal power and ground planes, utilizing the vertical dimension and internal layer space rather than consuming precious surface area.
Solution Approach 2:
The patent merges the capacitor formation process with the circuit board manufacturing process itself. The capacitive structure is integrated into the board's internal layers during lamination, combining the functions of board construction and capacitor installation into a single unified structure, eliminating the need for separate surface mounting operations.
2Reliability
If surface mounted capacitors are used to provide device-specific capacitance, then sufficient capacitance for high power devices is achieved, but inductance and resistance increase
Solution Approach 1:
The patent extracts the capacitor from the surface level and places it internally within the board structure. By removing the capacitor from the surface mounting position and embedding it between internal planes, the parasitic inductance and resistance associated with surface mounting paths are eliminated.
Solution Approach 2:
The patent moves the capacitive function from the surface dimension to the internal layer dimension. This dimensional transition allows the capacitor to be positioned much closer to the power pins in three-dimensional space, reducing the length of current paths and thereby minimizing parasitic inductance and resistance.
3Productivity
If integrated capacitive laminates are used to provide global power distribution, then capacitance is provided to multiple devices, but device-specific localized capacitance is insufficient
Solution Approach 1:
The patent applies local quality by creating a capacitive structure that is specifically positioned and dimensioned to serve a particular high-power device. The capacitor's location, size, and capacitance value are optimized for the specific device's power requirements rather than providing uniform global coverage.
Solution Approach 2:
The patent segments the power distribution network into global and local components. The integrated capacitive laminate provides global power distribution across the board, while the additional embedded capacitor is segmented to provide dedicated local capacitance specifically for high-power devices with elevated requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses voltage/current noise and resonances, increases high-frequency bypassing range, and saves surface space by eliminating the need for discrete capacitors, while maintaining the benefits of integrated capacitive laminates.
Implementation Method 1
a first dielectric layer having a first surface and an opposite second surface, a first conductive layer coupled to the first surface of the first dielectric layer, a second conductive layer coupled to the second surface of the first dielectric layer
Implementation Method 2
a resistive third conductive element, which reduces noise and interference
Data Source
AI summary
A multi-layered circuit board is provided having a buried capacitive layer and a device-specific embedded, localized, non-discrete, and distributive capacitive element. A printed circuit board is provided including (1) a first dielectric layer, (2) a first conductive layer coupled to a first surface of the first dielectric layer, (3) a second conductive layer coupled to a second surface of the first dielectric layer, and (4) a localized distributive non-discrete capacitive element adjacent the first conductive layer, wherein the capacitive element occupies a region that approximately coincides with a location over which a device to be coupled to the capacitive element is to be mounted. The embedded, localized, non-discrete, and distributive capacitive element may provide device-specific capacitance to suppress voltage/current noise for a particular device.