Embedded Logic FIFO Circuit for Full Clock-Period Utilization
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Solution Overview
Problem
Traditional flip-flop chain architectures in memory devices are inefficient in performing combination logic operations due to unavoidable time wastage in each stage, where either multiple stages must be completed in a single clock cycle or unused cycles occur when stages are mismatched with the number of logic stages.
Innovation Solution
A FIFO stack circuit with a combination logic circuit that includes an input ring counter circuit and an output ring counter circuit, allowing for high-speed combination logic operations by optimizing the timing of push and pop signals to utilize the full available clock periods, eliminating the need for multiple flip-flop stages and their associated delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If chained flip-flop architecture is used to perform combination logic operations, then the logic operations can be completed within defined latency periods, but time is wasted in each flip-flop stage due to setup time and clock signal delays
Solution Approach 1:
The patent divides the combination logic circuit into multiple pipeline stages, each stage processing a portion of the logic operations. By segmenting the logic circuit rather than using a single chained flip-flop architecture, the system reduces the time wasted in each stage while maintaining reliable timing through controlled pipeline registers at stage boundaries.
2Productivity
If the parity latency is greater than the number of logic stages, then additional clock periods are available, but the calculation cannot take advantage of the additional periods and results are simply passed from flip-flop to flip-flop
Solution Approach 1:
The patent implements dynamic pipeline staging where the number and configuration of pipeline stages can be adjusted based on the available latency periods. When additional clock periods are available, the system dynamically configures more pipeline stages to utilize those periods productively, rather than simply passing results through idle flip-flops. This dynamic adaptation maximizes productivity by matching the pipeline depth to the available time resources.
3Duration of action of moving object
If multiple logic stages must be completed during a single clock period, then the parity latency requirement is met, but the timing constraints become more stringent and difficult to satisfy
Solution Approach 1:
The patent segments the combination logic into multiple pipeline stages that can be executed sequentially across multiple clock periods. This segmentation allows the system to meet parity latency requirements without forcing multiple complex logic stages into a single clock period, thereby reducing timing constraint complexity while maintaining the required duration of action.
Data Source
AI summary
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.